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https://opencores.org/ocsvn/ram_wb/ram_wb/trunk
Subversion Repositories ram_wb
[/] [ram_wb/] [trunk/] [rtl/] [verilog/] [ram_wb_defines.v] - Rev 2
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`define RAM_WB_ADR_WIDTH 12 `define RAM_WB_MEM_SIZE 4096 `define RAM_WB_DAT_SIZE 32