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[/] [rv01_riscv_core/] [trunk/] [VHDL/] [RV01_divlog.vhd] - Rev 2
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----------------------------------------------------------------- -- -- ----------------------------------------------------------------- -- -- -- Copyright (C) 2015 Stefano Tonello -- -- -- -- This source file may be used and distributed without -- -- restriction provided that this copyright statement is not -- -- removed from the file and that any derivative work contains -- -- the original copyright notice and the associated disclaimer.-- -- -- -- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- -- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- -- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- -- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- -- POSSIBILITY OF SUCH DAMAGE. -- -- -- ----------------------------------------------------------------- --------------------------------------------------------------- -- RV01 division support logic --------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library WORK; use WORK.RV01_CONSTS_PKG.all; use WORK.RV01_TYPES_PKG.all; use WORK.RV01_ARITH_PKG.all; use work.RV01_IDEC_PKG.all; use work.RV01_OP_PKG.all; entity RV01_DIVLOG is port( V_i : in std_logic; INSTR_i : in DEC_INSTR_T; DIV_V_i : in std_logic; DIV_STRT_o : out std_logic; DIV_QS_o : out std_logic; DIV_CLRV_o : out std_logic ); end RV01_DIVLOG; architecture ARC of RV01_DIVLOG is begin -- Division start flag: a new division can start -- if current instruction is valid, is of -- division/reminder type and there's no result -- ready (if there's a result ready, instruction -- has been already re-fetched and therefore there -- is no need to re-execute it). DIV_STRT_o <= (V_i and not(DIV_V_i)) when ( INSTR_i.ALU_OP = ALU_DIV or INSTR_i.ALU_OP = ALU_REM ) else '0'; -- Division Quotient/Reminder result selection flag DIV_QS_o <= '1' when ( INSTR_i.ALU_OP = ALU_DIV ) else '0'; -- Clear division result valid flag: if current -- instruction is valid, is of division/reminder -- type and there's a result ready, result valid -- flag can be cleared. DIV_CLRV_o <= (V_i and DIV_V_i) when ( INSTR_i.ALU_OP = ALU_DIV or INSTR_i.ALU_OP = ALU_REM ) else '0'; end ARC;