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[/] [rv01_riscv_core/] [trunk/] [VHDL/] [RV01_queue.vhd] - Rev 2
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----------------------------------------------------------------- -- -- ----------------------------------------------------------------- -- -- -- Copyright (C) 2017 Stefano Tonello -- -- -- -- This source file may be used and distributed without -- -- restriction provided that this copyright statement is not -- -- removed from the file and that any derivative work contains -- -- the original copyright notice and the associated disclaimer.-- -- -- -- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- -- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- -- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- -- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- -- POSSIBILITY OF SUCH DAMAGE. -- -- -- ----------------------------------------------------------------- --------------------------------------------------------------- -- RV01 JALR Verification Queue --------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.RV01_CONSTS_PKG.all; use work.RV01_TYPES_PKG.all; use work.RV01_FUNCS_PKG.all; entity RV01_QUEUE is generic( DEPTH : natural := 2; WIDTH : natural := 32 ); port( CLK_i : in std_logic; RST_i : in std_logic; CLR_i : in std_logic; RE_i : in std_logic; WE_i : in std_logic; D_i : in std_logic_vector(WIDTH-1 downto 0); QE_o : out std_logic; QF_o : out std_logic; Q_o : out std_logic_vector(WIDTH-1 downto 0) ); end RV01_QUEUE; architecture ARC of RV01_QUEUE is subtype QUEUE_ENTRY_T is std_logic_vector(WIDTH-1 downto 0); type QUEUE_ENTRY_VEC_T is array (natural range<>) of QUEUE_ENTRY_T; signal Q,Q_q : QUEUE_ENTRY_VEC_T(DEPTH-1 downto 0); signal HP,HP_q : natural range 0 to DEPTH; signal QE_q,QF_q : std_logic; begin ------------------------------------ -- Head pointer registers. ------------------------------------ process(CLK_i) begin if(CLK_i = '1' and CLK_i'event) then if(RST_i = '1' or CLR_i = '1') then HP_q <= 0; elsif(WE_i = '1' and RE_i = '0') then HP_q <= HP_q + 1; elsif(RE_i = '1' and WE_i = '0') then HP_q <= HP_q - 1; end if; end if; end process; ------------------------------------ -- Queue update logic. ------------------------------------ process(Q_q,HP_q,RE_i,WE_i,D_i) begin for k in 0 to DEPTH-1 loop Q(k) <= Q_q(k); if(RE_i = '1') then if(k < DEPTH-1) then Q(k) <= Q_q(k+1); else Q(k) <= (others => '0'); end if; end if; if(WE_i = '1' and RE_i = '0') then if(k = HP_q) then Q(k) <= D_i; end if; elsif(WE_i = '1' and RE_i = '1') then if(k = HP_q-1) then Q(k) <= D_i; end if; end if; end loop; end process; ------------------------------------ -- Queue registers. ------------------------------------ process(CLK_i) begin if(CLK_i = '1' and CLK_i'event) then for k in 0 to DEPTH-1 loop Q_q(k) <= Q(k); end loop; end if; end process; ------------------------------------ -- Queue Empty flag register. ------------------------------------ process(CLK_i) begin if(CLK_i = '1' and CLK_i'event) then if(RST_i = '1' or CLR_i = '1') then QE_q <= '0'; elsif((HP_q = 0 and WE_i = '0') or (HP_q = 1 and RE_i = '1')) then QE_q <= '1'; else QE_q <= '0'; end if; end if; end process; ------------------------------------ -- Queue Full flag register. ------------------------------------ process(CLK_i) begin if(CLK_i = '1' and CLK_i'event) then if(RST_i = '1' or CLR_i = '1') then QF_q <= '0'; elsif((HP_q = DEPTH and RE_i = '0') or (HP_q = DEPTH-1 and WE_i = '1')) then QF_q <= '1'; else QF_q <= '0'; end if; end if; end process; ------------------------------------ -- Outputs ------------------------------------ QE_o <= QE_q; QF_o <= QF_q; Q_o <= Q_q(0); end ARC;