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[/] [rv01_riscv_core/] [trunk/] [VHDL/] [RV01_top_nohost.vhd] - Rev 2
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----------------------------------------------------------------- -- -- ----------------------------------------------------------------- -- -- -- Copyright (C) 2017 Stefano Tonello -- -- -- -- This source file may be used and distributed without -- -- restriction provided that this copyright statement is not -- -- removed from the file and that any derivative work contains -- -- the original copyright notice and the associated disclaimer.-- -- -- -- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- -- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- -- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- -- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- -- POSSIBILITY OF SUCH DAMAGE. -- -- -- ----------------------------------------------------------------- --------------------------------------------------------------- -- RV01 top-level module (without host interface) --------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use STD.textio.all; library WORK; use work.RV01_CONSTS_PKG.all; use work.RV01_TYPES_PKG.all; use work.RV01_FUNCS_PKG.all; use work.RV01_PLIC_PKG.all; entity RV01_TOP_NOHOST is generic( -- synthesis translate_off ST_FILE : string := "NONE"; WB_FILE : string := "NONE"; -- synthesis translate_on IMEM_SIZE : natural := 1024*32; -- 128Kb DMEM_SIZE : natural := 1024*16; -- 64Kb IOMEM_SIZE : natural := 1024; -- 4Kb IMEM_SIZE_PO2 : std_logic := '1'; DMEM_SIZE_PO2 : std_logic := '1'; IMEM_LOWM : std_logic := '1'; BHT_SIZE : natural := 256; EI_SRC_CNT : natural := 8; EI_TRIG_TYPE : PLIC_TRIG_TYPE := LEVEL; EI_REQ_MAXCNT : natural := 16; CFG_FLAGS : std_logic_vector(16-1 downto 0) := "00000000"&"01100111"; SIMULATION_ONLY : std_logic := '0' ); port( CLK_i : in std_logic; -- clock RST_i : in std_logic; -- reset -- External Interrupt Request EI_REQ_i : std_logic_vector(EI_SRC_CNT-1 downto 0); -- DP Port DP_WE_i : in std_logic; -- DP write-enable DP_ADR_i : in std_logic_vector(ALEN-1 downto 0); -- DP address DP_DAT_i : in std_logic_vector(SDLEN-1 downto 0); -- DP data-in -- Control Port CP_RE_i : in std_logic; -- CP read-enable CP_WE_i : in std_logic; -- CP write enable CP_ADR_i : in std_logic_vector(17-1 downto 0); -- CP address CP_DAT_i : in std_logic_vector(SDLEN-1 downto 0); -- CP data-in -- DP interface DP_DAT_o : out std_logic_vector(SDLEN-1 downto 0); -- DP data-out -- CP interface CP_DAT_o : out std_logic_vector(SDLEN-1 downto 0) -- CP data-out ); end RV01_TOP_NOHOST; architecture ARC of RV01_TOP_NOHOST is component RV01_TOP is generic( -- synthesis translate_off ST_FILE : string := "NONE"; WB_FILE : string := "NONE"; -- synthesis translate_on IMEM_SIZE : natural := 1024*32; -- 128Kb DMEM_SIZE : natural := 1024*16; -- 64Kb IOMEM_SIZE : natural := 1024; -- 4Kb IMEM_SIZE_PO2 : std_logic := '1'; DMEM_SIZE_PO2 : std_logic := '1'; IMEM_LOWM : std_logic := '1'; BHT_SIZE : natural := 256; EI_SRC_CNT : natural := 8; EI_TRIG_TYPE : PLIC_TRIG_TYPE := LEVEL; EI_REQ_MAXCNT : natural := 16; CFG_FLAGS : std_logic_vector(16-1 downto 0) := "00000000"&"01100111"; SIMULATION_ONLY : std_logic := '0' ); port( CLK_i : in std_logic; -- clock RST_i : in std_logic; -- reset CHK_ENB_i : in std_logic; -- check-enable -- External Interrupt Request EI_REQ_i : std_logic_vector(EI_SRC_CNT-1 downto 0); -- Host interface MFROMHOST_WE_i : in std_logic; MFROMHOST_i : in std_logic_vector(SDLEN-1 downto 0); -- DP interface DP_WE_i : in std_logic; -- DP write-enable DP_ADR_i : in std_logic_vector(ALEN-1 downto 0); DP_DAT_i : in std_logic_vector(SDLEN-1 downto 0); -- DP data-in -- CP interface CP_RE_i : in std_logic; CP_WE_i : in std_logic; CP_ADR_i : in std_logic_vector(17-1 downto 0); CP_DAT_i : in std_logic_vector(SDLEN-1 downto 0); -- Host interface MTOHOST_OE_o : out std_logic; MTOHOST_o : out std_logic_vector(SDLEN-1 downto 0); -- DP interface DP_DAT_o : out std_logic_vector(SDLEN-1 downto 0); -- DP data-out -- CP interface CP_DAT_o : out std_logic_vector(SDLEN-1 downto 0) ); end component ; constant PLIC_PRESENT : std_logic := CFG_FLAGS(6); signal CHK_ENB : std_logic := '1'; signal EI_REQ : std_logic_vector(EI_SRC_CNT-1 downto 0); signal MFROMHOST_WE : std_logic; signal MFROMHOST : std_logic_vector(SDLEN-1 downto 0) := (others => '0'); signal MTOHOST_OE : std_logic; signal MTOHOST : std_logic_vector(SDLEN-1 downto 0); signal MHOST_V_q : std_logic; signal MHOST_q : std_logic_vector(SDLEN-1 downto 0); begin ---------------------------------------------- -- This module exists mainly as a debugging -- and simulation aid, it consists of an -- instance of the top-level module RV01_TOP -- with the MTOHOST_o output looping back to -- the MFROMHOST_i and EI_REQ_i inputs. -- This arrangement allows to simulate the -- host interface and, to some degree, PLIC -- module operations without additional logic. ---------------------------------------------- U_RVTOP : RV01_TOP generic map( -- synthesis translate_off ST_FILE => ST_FILE, --"NONE", WB_FILE => WB_FILE, --"NONE", -- synthesis translate_on IMEM_SIZE => IMEM_SIZE, DMEM_SIZE => DMEM_SIZE, IOMEM_SIZE => IOMEM_SIZE, IMEM_SIZE_PO2 => IMEM_SIZE_PO2, DMEM_SIZE_PO2 => DMEM_SIZE_PO2, IMEM_LOWM => IMEM_LOWM, BHT_SIZE => BHT_SIZE, EI_SRC_CNT => EI_SRC_CNT, EI_TRIG_TYPE => EI_TRIG_TYPE, EI_REQ_MAXCNT => EI_REQ_MAXCNT, CFG_FLAGS => CFG_FLAGS, SIMULATION_ONLY => SIMULATION_ONLY ) port map( CLK_i => CLK_i, RST_i => RST_i, CHK_ENB_i => CHK_ENB, -- EI_REQ_i => EI_REQ, -- MFROMHOST_WE_i => MFROMHOST_WE, MFROMHOST_i => MFROMHOST, -- DP_WE_i => DP_WE_i, DP_ADR_i => DP_ADR_i, DP_DAT_i => DP_DAT_i, -- CP_RE_i => CP_RE_i, CP_WE_i => CP_WE_i, CP_ADR_i => CP_ADR_i, CP_DAT_i => CP_DAT_i, MTOHOST_OE_o => MTOHOST_OE, MTOHOST_o => MTOHOST, -- DP_DAT_o => DP_DAT_o, -- CP_DAT_o => CP_DAT_o ); -- Looping-back MTOHOST into MFROMHOST: this -- provides a simple way of checking host -- insterface. process(CLK_i) begin if(CLK_i = '1' and CLK_i'event) then if(RST_i = '1') then MHOST_V_q <= '0'; else MHOST_V_q <= MTOHOST_OE; end if; MHOST_q <= MTOHOST; end if; end process; MFROMHOST_WE <= MHOST_V_q; MFROMHOST <= MHOST_q; -- Drive EI_REQ through MTOHOST: this -- provides a simple way of generating -- external interrupt requests. GPLIC_1: if(PLIC_PRESENT = '1') generate EI_REQ <= MTOHOST(EI_SRC_CNT-1 downto 0) or EI_REQ_i; end generate; GPLIC_0: if(PLIC_PRESENT = '0') generate EI_REQ <= (others => '0'); end generate; end ARC;