OpenCores
URL https://opencores.org/ocsvn/s80186/s80186/trunk

Subversion Repositories s80186

[/] [s80186/] [trunk/] [rtl/] [microcode/] [esc.us] - Rev 2

Compare with Previous | Blame | View Log

// Copyright Jamie Iles, 2017
//
// This file is part of s80x86.
//
// s80x86 is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// s80x86 is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with s80x86.  If not, see <http://www.gnu.org/licenses/>.

#include <config.h>

.at 0xd8;
    modrm_start, jmp do_esc;
.at 0xd9;
    modrm_start, jmp do_esc;
.at 0xda;
    modrm_start, jmp do_esc;
.at 0xdb;
    modrm_start, jmp do_esc;
.at 0xdc;
    modrm_start, jmp do_esc;
.at 0xdd;
    modrm_start, jmp do_esc;
.at 0xde;
    modrm_start, jmp do_esc;
.at 0xdf;
    modrm_start, jmp do_esc;

.auto_address;
do_esc:
#if (S80X86_TRAP_ESCAPE == 1)
    b_sel IMMEDIATE, immediate 0x1c, alu_op SELB, tmp_wr_en, jmp do_int;
#else
    next_instruction;
#endif

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.