URL
https://opencores.org/ocsvn/sata_controller_core/sata_controller_core/trunk
Subversion Repositories sata_controller_core
[/] [sata_controller_core/] [trunk/] [sata2_fifo_v1_00_a/] [hdl/] [verilog/] [mgt_usrclk_source_mmcm.v] - Rev 17
Go to most recent revision | Compare with Previous | Blame | View Log
/////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version : 1.8 // \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard // / / Filename : mgt_usrclk_source_mmcm.v // /___/ /\ Timestamp : // \ \ / \ // \___\/\___\ // // // Module MGT_USRCLK_SOURCE (for use with GTX Transceivers) // Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard // // // (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. `timescale 1ns / 1ps //***********************************Entity Declaration******************************* module MGT_USRCLK_SOURCE_MMCM # ( parameter MULT = 2, parameter DIVIDE = 2, parameter CLK_PERIOD = 6.4, parameter OUT0_DIVIDE = 2, parameter OUT1_DIVIDE = 2, parameter OUT2_DIVIDE = 2, parameter OUT3_DIVIDE = 2 ) ( output CLK0_OUT, output CLK1_OUT, output CLK2_OUT, output CLK3_OUT, input CLK_IN, output MMCM_LOCKED_OUT, input MMCM_RESET_IN ); `define DLY #1 //*********************************Wire Declarations********************************** wire [15:0] tied_to_ground_vec_i; wire tied_to_ground_i; wire clkout0_i; wire clkout1_i; wire clkout2_i; wire clkout3_i; wire clkfbout_i; //*********************************** Beginning of Code ******************************* // Static signal Assigments assign tied_to_ground_i = 1'b0; assign tied_to_ground_vec_i = 16'h0000; // Instantiate a MMCM module to divide the reference clock. Uses internal feedback // for improved jitter performance, and to avoid consuming an additional BUFG MMCM_ADV # ( .COMPENSATION ("ZHOLD"), .CLKFBOUT_MULT_F (MULT), .DIVCLK_DIVIDE (DIVIDE), .CLKFBOUT_PHASE (0), .CLKIN1_PERIOD (CLK_PERIOD), .CLKIN2_PERIOD (10), //Not used .CLKOUT0_DIVIDE_F (OUT0_DIVIDE), .CLKOUT0_PHASE (0), .CLKOUT1_DIVIDE (OUT1_DIVIDE), .CLKOUT1_PHASE (0), .CLKOUT2_DIVIDE (OUT2_DIVIDE), .CLKOUT2_PHASE (0), .CLKOUT3_DIVIDE (OUT3_DIVIDE), .CLKOUT3_PHASE (0), .CLOCK_HOLD ("TRUE") ) mmcm_adv_i ( .CLKIN1 (CLK_IN), .CLKIN2 (1'b0), .CLKINSEL (1'b1), .CLKFBIN (clkfbout_i), .CLKOUT0 (clkout0_i), .CLKOUT0B (), .CLKOUT1 (clkout1_i), .CLKOUT1B (), .CLKOUT2 (clkout2_i), .CLKOUT2B (), .CLKOUT3 (clkout3_i), .CLKOUT3B (), .CLKOUT4 (), .CLKOUT5 (), .CLKOUT6 (), .CLKFBOUT (clkfbout_i), .CLKFBOUTB (), .CLKFBSTOPPED (), .CLKINSTOPPED (), .DO (), .DRDY (), .DADDR (7'd0), .DCLK (1'b0), .DEN (1'b0), .DI (16'd0), .DWE (1'b0), .LOCKED (MMCM_LOCKED_OUT), .PSCLK (1'b0), .PSEN (1'b0), .PSINCDEC (1'b0), .PSDONE (), .PWRDWN (1'b0), .RST (MMCM_RESET_IN) ); BUFG clkout0_bufg_i ( .O (CLK0_OUT), .I (clkout0_i) ); BUFG clkout1_bufg_i ( .O (CLK1_OUT), .I (clkout1_i) ); BUFG clkout2_bufg_i ( .O (CLK2_OUT), .I (clkout2_i) ); BUFG clkout3_bufg_i ( .O (CLK3_OUT), .I (clkout3_i) ); endmodule
Go to most recent revision | Compare with Previous | Blame | View Log