URL
https://opencores.org/ocsvn/scarts/scarts/trunk
Subversion Repositories scarts
[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [bclslr.cgs] - Rev 26
Compare with Previous | Blame | View Log
# frv testcase for bclslr $ICCi,$ccond,$hint# mach: all.include "testutils.inc"start.global bclslrbclslr:; ccond is trueset_spr_immed 128,lcrset_spr_addr bad,lrset_icc 0x0 0bclslr icc0,0,0set_spr_addr ok2,lrset_icc 0x1 1bclslr icc1,0,1failok2:set_spr_addr bad,lrset_icc 0x2 2bclslr icc2,0,2set_spr_addr ok4,lrset_icc 0x3 3bclslr icc3,0,3failok4:set_spr_addr ok5,lrset_icc 0x4 0bclslr icc0,0,0failok5:set_spr_addr ok6,lrset_icc 0x5 1bclslr icc1,0,1failok6:set_spr_addr ok7,lrset_icc 0x6 2bclslr icc2,0,2failok7:set_spr_addr ok8,lrset_icc 0x7 3bclslr icc3,0,3failok8:set_spr_addr bad,lrset_icc 0x8 0bclslr icc0,0,0set_spr_addr oka,lrset_icc 0x9 1bclslr icc1,0,1failoka:set_spr_addr bad,lrset_icc 0xa 2bclslr icc2,0,2set_spr_addr okc,lrset_icc 0xb 3bclslr icc3,0,3failokc:set_spr_addr okd,lrset_icc 0xc 0bclslr icc0,0,0failokd:set_spr_addr oke,lrset_icc 0xd 1bclslr icc1,0,1failoke:set_spr_addr okf,lrset_icc 0xe 2bclslr icc2,0,2failokf:set_spr_addr okg,lrset_icc 0xf 3bclslr icc3,0,3failokg:; ccond is trueset_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x0 0bclslr icc0,1,0set_spr_immed 1,lcrset_spr_addr oki,lrset_icc 0x1 1bclslr icc1,1,1failoki:set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x2 2bclslr icc2,1,2set_spr_immed 1,lcrset_spr_addr okk,lrset_icc 0x3 3bclslr icc3,1,3failokk:set_spr_immed 1,lcrset_spr_addr okl,lrset_icc 0x4 0bclslr icc0,1,0failokl:set_spr_immed 1,lcrset_spr_addr okm,lrset_icc 0x5 1bclslr icc1,1,1failokm:set_spr_immed 1,lcrset_spr_addr okn,lrset_icc 0x6 2bclslr icc2,1,2failokn:set_spr_immed 1,lcrset_spr_addr oko,lrset_icc 0x7 3bclslr icc3,1,3failoko:set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x8 0bclslr icc0,1,0set_spr_immed 1,lcrset_spr_addr okq,lrset_icc 0x9 1bclslr icc1,1,1failokq:set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0xa 2bclslr icc2,1,2set_spr_immed 1,lcrset_spr_addr oks,lrset_icc 0xb 3bclslr icc3,1,3failoks:set_spr_immed 1,lcrset_spr_addr okt,lrset_icc 0xc 0bclslr icc0,1,0failokt:set_spr_immed 1,lcrset_spr_addr oku,lrset_icc 0xd 1bclslr icc1,1,1failoku:set_spr_immed 1,lcrset_spr_addr okv,lrset_icc 0xe 2bclslr icc2,1,2failokv:set_spr_immed 1,lcrset_spr_addr okw,lrset_icc 0xf 3bclslr icc3,1,3failokw:; ccond is falseset_spr_immed 128,lcrset_spr_addr bad,lrset_icc 0x0 0bclslr icc0,1,0set_icc 0x1 1bclslr icc1,1,1set_icc 0x2 2bclslr icc2,1,2set_icc 0x3 3bclslr icc3,1,3set_icc 0x4 0bclslr icc0,1,0set_icc 0x5 1bclslr icc1,1,1set_icc 0x6 2bclslr icc2,1,2set_icc 0x7 3bclslr icc3,1,3set_icc 0x8 0bclslr icc0,1,0set_icc 0x9 1bclslr icc1,1,1set_icc 0xa 2bclslr icc2,1,2set_icc 0xb 3bclslr icc3,1,3set_icc 0xc 0bclslr icc0,1,0set_icc 0xd 1bclslr icc1,1,1set_icc 0xe 2bclslr icc2,1,2set_icc 0xf 3bclslr icc3,1,3; ccond is falseset_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x0 0bclslr icc0,0,0set_spr_immed 1,lcrset_icc 0x1 1bclslr icc1,0,1set_spr_immed 1,lcrset_icc 0x2 2bclslr icc2,0,2set_spr_immed 1,lcrset_icc 0x3 3bclslr icc3,0,3set_spr_immed 1,lcrset_icc 0x4 0bclslr icc0,0,0set_spr_immed 1,lcrset_icc 0x5 1bclslr icc1,0,1set_spr_immed 1,lcrset_icc 0x6 2bclslr icc2,0,2set_spr_immed 1,lcrset_icc 0x7 3bclslr icc3,0,3set_spr_immed 1,lcrset_icc 0x8 0bclslr icc0,0,0set_spr_immed 1,lcrset_icc 0x9 1bclslr icc1,0,1set_spr_immed 1,lcrset_icc 0xa 2bclslr icc2,0,2set_spr_immed 1,lcrset_icc 0xb 3bclslr icc3,0,3set_spr_immed 1,lcrset_icc 0xc 0bclslr icc0,0,0set_spr_immed 1,lcrset_icc 0xd 1bclslr icc1,0,1set_spr_immed 1,lcrset_icc 0xe 2bclslr icc2,0,2set_spr_immed 1,lcrset_icc 0xf 3bclslr icc3,0,3passbad:fail