URL
https://opencores.org/ocsvn/scarts/scarts/trunk
Subversion Repositories scarts
[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [bcltlr.cgs] - Rev 26
Compare with Previous | Blame | View Log
# frv testcase for bcltlr $ICCi,$ccond,$hint# mach: all.include "testutils.inc"start.global bcltlrbcltlr:; ccond is trueset_spr_immed 128,lcrset_spr_addr bad,lrset_icc 0x0 0bcltlr icc0,0,0set_spr_addr bad,lrset_icc 0x1 1bcltlr icc1,0,1set_spr_addr ok3,lrset_icc 0x2 2bcltlr icc2,0,2failok3:set_spr_addr ok4,lrset_icc 0x3 3bcltlr icc3,0,3failok4:set_spr_addr bad,lrset_icc 0x4 0bcltlr icc0,0,0set_spr_addr bad,lrset_icc 0x5 1bcltlr icc1,0,1set_spr_addr ok7,lrset_icc 0x6 2bcltlr icc2,0,2failok7:set_spr_addr ok8,lrset_icc 0x7 3bcltlr icc3,0,3failok8:set_spr_addr ok9,lrset_icc 0x8 0bcltlr icc0,0,0failok9:set_spr_addr oka,lrset_icc 0x9 1bcltlr icc1,0,1failoka:set_spr_addr bad,lrset_icc 0xa 2bcltlr icc2,0,2set_spr_addr bad,lrset_icc 0xb 3bcltlr icc3,0,3set_spr_addr okd,lrset_icc 0xc 0bcltlr icc0,0,0failokd:set_spr_addr oke,lrset_icc 0xd 1bcltlr icc1,0,1failoke:set_spr_addr bad,lrset_icc 0xe 2bcltlr icc2,0,2set_spr_addr bad,lrset_icc 0xf 3bcltlr icc3,0,3; ccond is trueset_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x0 0bcltlr icc0,1,0set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x1 1bcltlr icc1,1,1set_spr_immed 1,lcrset_spr_addr okj,lrset_icc 0x2 2bcltlr icc2,1,2failokj:set_spr_immed 1,lcrset_spr_addr okk,lrset_icc 0x3 3bcltlr icc3,1,3failokk:set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x4 0bcltlr icc0,1,0set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x5 1bcltlr icc1,1,1set_spr_immed 1,lcrset_spr_addr okn,lrset_icc 0x6 2bcltlr icc2,1,2failokn:set_spr_immed 1,lcrset_spr_addr oko,lrset_icc 0x7 3bcltlr icc3,1,3failoko:set_spr_immed 1,lcrset_spr_addr okp,lrset_icc 0x8 0bcltlr icc0,1,0failokp:set_spr_immed 1,lcrset_spr_addr okq,lrset_icc 0x9 1bcltlr icc1,1,1failokq:set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0xa 2bcltlr icc2,1,2set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0xb 3bcltlr icc3,1,3set_spr_immed 1,lcrset_spr_addr okt,lrset_icc 0xc 0bcltlr icc0,1,0failokt:set_spr_immed 1,lcrset_spr_addr oku,lrset_icc 0xd 1bcltlr icc1,1,1failoku:set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0xe 2bcltlr icc2,1,2set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0xf 3bcltlr icc3,1,3; ccond is falseset_spr_immed 128,lcrset_spr_addr bad,lrset_icc 0x0 0bcltlr icc0,1,0set_icc 0x1 1bcltlr icc1,1,1set_icc 0x2 2bcltlr icc2,1,2set_icc 0x3 3bcltlr icc3,1,3set_icc 0x4 0bcltlr icc0,1,0set_icc 0x5 1bcltlr icc1,1,1set_icc 0x6 2bcltlr icc2,1,2set_icc 0x7 3bcltlr icc3,1,3set_icc 0x8 0bcltlr icc0,1,0set_icc 0x9 1bcltlr icc1,1,1set_icc 0xa 2bcltlr icc2,1,2set_icc 0xb 3bcltlr icc3,1,3set_icc 0xc 0bcltlr icc0,1,0set_icc 0xd 1bcltlr icc1,1,1set_icc 0xe 2bcltlr icc2,1,2set_icc 0xf 3bcltlr icc3,1,3; ccond is falseset_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x0 0bcltlr icc0,0,0set_spr_immed 1,lcrset_icc 0x1 1bcltlr icc1,0,1set_spr_immed 1,lcrset_icc 0x2 2bcltlr icc2,0,2set_spr_immed 1,lcrset_icc 0x3 3bcltlr icc3,0,3set_spr_immed 1,lcrset_icc 0x4 0bcltlr icc0,0,0set_spr_immed 1,lcrset_icc 0x5 1bcltlr icc1,0,1set_spr_immed 1,lcrset_icc 0x6 2bcltlr icc2,0,2set_spr_immed 1,lcrset_icc 0x7 3bcltlr icc3,0,3set_spr_immed 1,lcrset_icc 0x8 0bcltlr icc0,0,0set_spr_immed 1,lcrset_icc 0x9 1bcltlr icc1,0,1set_spr_immed 1,lcrset_icc 0xa 2bcltlr icc2,0,2set_spr_immed 1,lcrset_icc 0xb 3bcltlr icc3,0,3set_spr_immed 1,lcrset_icc 0xc 0bcltlr icc0,0,0set_spr_immed 1,lcrset_icc 0xd 1bcltlr icc1,0,1set_spr_immed 1,lcrset_icc 0xe 2bcltlr icc2,0,2set_spr_immed 1,lcrset_icc 0xf 3bcltlr icc3,0,3passbad:fail