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https://opencores.org/ocsvn/scarts/scarts/trunk
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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fcbeqlr.cgs] - Rev 26
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# frv testcase for fcbeqlr $FCCi,$ccond,$hint# mach: all.include "testutils.inc"start.global fcbeqlrfcbeqlr:; ccond is trueset_spr_immed 128,lcrset_spr_addr bad,lrset_fcc 0x0 0fcbeqlr fcc0,0,0set_spr_addr bad,lrset_fcc 0x1 1fcbeqlr fcc1,0,1set_spr_addr bad,lrset_fcc 0x2 2fcbeqlr fcc2,0,2set_spr_addr bad,lrset_fcc 0x3 3fcbeqlr fcc3,0,3set_spr_addr bad,lrset_fcc 0x4 0fcbeqlr fcc0,0,0set_spr_addr bad,lrset_fcc 0x5 1fcbeqlr fcc1,0,1set_spr_addr bad,lrset_fcc 0x6 2fcbeqlr fcc2,0,2set_spr_addr bad,lrset_fcc 0x7 3fcbeqlr fcc3,0,3set_spr_addr ok9,lrset_fcc 0x8 0fcbeqlr fcc0,0,0failok9:set_spr_addr oka,lrset_fcc 0x9 1fcbeqlr fcc1,0,1failoka:set_spr_addr okb,lrset_fcc 0xa 2fcbeqlr fcc2,0,2failokb:set_spr_addr okc,lrset_fcc 0xb 3fcbeqlr fcc3,0,3failokc:set_spr_addr okd,lrset_fcc 0xc 0fcbeqlr fcc0,0,0failokd:set_spr_addr oke,lrset_fcc 0xd 1fcbeqlr fcc1,0,1failoke:set_spr_addr okf,lrset_fcc 0xe 2fcbeqlr fcc2,0,2failokf:set_spr_addr okg,lrset_fcc 0xf 3fcbeqlr fcc3,0,3failokg:; ccond is trueset_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x0 0fcbeqlr fcc0,1,0set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x1 1fcbeqlr fcc1,1,1set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x2 2fcbeqlr fcc2,1,2set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x3 3fcbeqlr fcc3,1,3set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x4 0fcbeqlr fcc0,1,0set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x5 1fcbeqlr fcc1,1,1set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x6 2fcbeqlr fcc2,1,2set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x7 3fcbeqlr fcc3,1,3set_spr_immed 1,lcrset_spr_addr okp,lrset_fcc 0x8 0fcbeqlr fcc0,1,0failokp:set_spr_immed 1,lcrset_spr_addr okq,lrset_fcc 0x9 1fcbeqlr fcc1,1,1failokq:set_spr_immed 1,lcrset_spr_addr okr,lrset_fcc 0xa 2fcbeqlr fcc2,1,2failokr:set_spr_immed 1,lcrset_spr_addr oks,lrset_fcc 0xb 3fcbeqlr fcc3,1,3failoks:set_spr_immed 1,lcrset_spr_addr okt,lrset_fcc 0xc 0fcbeqlr fcc0,1,0failokt:set_spr_immed 1,lcrset_spr_addr oku,lrset_fcc 0xd 1fcbeqlr fcc1,1,1failoku:set_spr_immed 1,lcrset_spr_addr okv,lrset_fcc 0xe 2fcbeqlr fcc2,1,2failokv:set_spr_immed 1,lcrset_spr_addr okw,lrset_fcc 0xf 3fcbeqlr fcc3,1,3failokw:; ccond is falseset_spr_immed 128,lcrset_fcc 0x0 0fcbeqlr fcc0,1,0set_fcc 0x1 1fcbeqlr fcc1,1,1set_fcc 0x2 2fcbeqlr fcc2,1,2set_fcc 0x3 3fcbeqlr fcc3,1,3set_fcc 0x4 0fcbeqlr fcc0,1,0set_fcc 0x5 1fcbeqlr fcc1,1,1set_fcc 0x6 2fcbeqlr fcc2,1,2set_fcc 0x7 3fcbeqlr fcc3,1,3set_fcc 0x8 0fcbeqlr fcc0,1,0set_fcc 0x9 1fcbeqlr fcc1,1,1set_fcc 0xa 2fcbeqlr fcc2,1,2set_fcc 0xb 3fcbeqlr fcc3,1,3set_fcc 0xc 0fcbeqlr fcc0,1,0set_fcc 0xd 1fcbeqlr fcc1,1,1set_fcc 0xe 2fcbeqlr fcc2,1,2set_fcc 0xf 3fcbeqlr fcc3,1,3; ccond is falseset_spr_immed 1,lcrset_fcc 0x0 0fcbeqlr fcc0,0,0set_spr_immed 1,lcrset_fcc 0x1 1fcbeqlr fcc1,0,1set_spr_immed 1,lcrset_fcc 0x2 2fcbeqlr fcc2,0,2set_spr_immed 1,lcrset_fcc 0x3 3fcbeqlr fcc3,0,3set_spr_immed 1,lcrset_fcc 0x4 0fcbeqlr fcc0,0,0set_spr_immed 1,lcrset_fcc 0x5 1fcbeqlr fcc1,0,1set_spr_immed 1,lcrset_fcc 0x6 2fcbeqlr fcc2,0,2set_spr_immed 1,lcrset_fcc 0x7 3fcbeqlr fcc3,0,3set_spr_immed 1,lcrset_fcc 0x8 0fcbeqlr fcc0,0,0set_spr_immed 1,lcrset_fcc 0x9 1fcbeqlr fcc1,0,1set_spr_immed 1,lcrset_fcc 0xa 2fcbeqlr fcc2,0,2set_spr_immed 1,lcrset_fcc 0xb 3fcbeqlr fcc3,0,3set_spr_immed 1,lcrset_fcc 0xc 0fcbeqlr fcc0,0,0set_spr_immed 1,lcrset_fcc 0xd 1fcbeqlr fcc1,0,1set_spr_immed 1,lcrset_fcc 0xe 2fcbeqlr fcc2,0,2set_spr_immed 1,lcrset_fcc 0xf 3fcbeqlr fcc3,0,3passbad:fail