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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fr550/] [cmmachu.cgs] - Rev 26
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# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond# mach: all.include "../testutils.inc"start.global cmmachucmmachu:set_spr_immed 0x1b1b,cccrset_spr_immed 0,msr0set_accg_immed 0,accg0set_acc_immed 0,acc0set_accg_immed 0,accg1set_acc_immed 0,acc1set_fr_iimmed 3,2,fr7 ; multiply small numbersset_fr_iimmed 2,3,fr8cmmachu fr7,fr8,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 6,acc0test_accg_immed 0,accg1test_acc_immed 6,acc1set_fr_iimmed 1,2,fr7 ; multiply by 1set_fr_iimmed 2,1,fr8cmmachu fr7,fr8,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 8,acc0test_accg_immed 0,accg1test_acc_immed 8,acc1set_fr_iimmed 0,2,fr7 ; multiply by 0set_fr_iimmed 2,0,fr8cmmachu fr7,fr8,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 8,acc0test_accg_immed 0,accg1test_acc_immed 8,acc1set_fr_iimmed 0x3fff,2,fr7 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr8cmmachu fr7,fr8,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_limmed 0x0000,0x8006,acc0test_accg_immed 0,accg1test_acc_limmed 0x0000,0x8006,acc1set_fr_iimmed 0x4000,2,fr7 ; 16 bit resultset_fr_iimmed 2,0x4000,fr8cmmachu fr7,fr8,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_limmed 0x0001,0x0006,acc0test_accg_immed 0,accg1test_acc_limmed 0x0001,0x0006,acc1set_fr_iimmed 0x8000,2,fr7 ; 17 bit resultset_fr_iimmed 2,0x8000,fr8cmmachu fr7,fr8,acc0,cc4,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 0x00020006,acc0test_accg_immed 0,accg1test_acc_immed 0x00020006,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr8cmmachu fr7,fr8,acc0,cc4,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 0x40010007,acc0test_accg_immed 0,accg1test_acc_immed 0x40010007,acc1set_fr_iimmed 0x8000,0x8000,fr7 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr8cmmachu fr7,fr8,acc0,cc4,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_limmed 0x8001,0x0007,acc0test_accg_immed 0,accg1test_acc_limmed 0x8001,0x0007,acc1set_fr_iimmed 0xffff,0xffff,fr7 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr8cmmachu fr7,fr8,acc0,cc4,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 1,accg0test_acc_limmed 0x7fff,0x0008,acc0test_accg_immed 1,accg1test_acc_limmed 0x7fff,0x0008,acc1set_accg_immed 0xff,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0xff,accg1set_acc_immed 0xffffffff,acc1set_fr_iimmed 1,1,fr7set_fr_iimmed 1,1,fr8cmmachu fr7,fr8,acc0,cc4,1test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xffff,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xffff,acc1set_fr_iimmed 0xffff,0x0000,fr7set_fr_iimmed 0xffff,0xffff,fr8cmmachu fr7,fr8,acc0,cc4,1test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xffff,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xffff,acc1set_spr_immed 0,msr0set_accg_immed 0,accg0set_acc_immed 0,acc0set_accg_immed 0,accg1set_acc_immed 0,acc1set_fr_iimmed 3,2,fr7 ; multiply small numbersset_fr_iimmed 2,3,fr8cmmachu fr7,fr8,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 6,acc0test_accg_immed 0,accg1test_acc_immed 6,acc1set_fr_iimmed 1,2,fr7 ; multiply by 1set_fr_iimmed 2,1,fr8cmmachu fr7,fr8,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 8,acc0test_accg_immed 0,accg1test_acc_immed 8,acc1set_fr_iimmed 0,2,fr7 ; multiply by 0set_fr_iimmed 2,0,fr8cmmachu fr7,fr8,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 8,acc0test_accg_immed 0,accg1test_acc_immed 8,acc1set_fr_iimmed 0x3fff,2,fr7 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr8cmmachu fr7,fr8,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_limmed 0x0000,0x8006,acc0test_accg_immed 0,accg1test_acc_limmed 0x0000,0x8006,acc1set_fr_iimmed 0x4000,2,fr7 ; 16 bit resultset_fr_iimmed 2,0x4000,fr8cmmachu fr7,fr8,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_limmed 0x0001,0x0006,acc0test_accg_immed 0,accg1test_acc_limmed 0x0001,0x0006,acc1set_fr_iimmed 0x8000,2,fr7 ; 17 bit resultset_fr_iimmed 2,0x8000,fr8cmmachu fr7,fr8,acc0,cc5,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 0x00020006,acc0test_accg_immed 0,accg1test_acc_immed 0x00020006,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr8cmmachu fr7,fr8,acc0,cc5,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 0x40010007,acc0test_accg_immed 0,accg1test_acc_immed 0x40010007,acc1set_fr_iimmed 0x8000,0x8000,fr7 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr8cmmachu fr7,fr8,acc0,cc5,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_limmed 0x8001,0x0007,acc0test_accg_immed 0,accg1test_acc_limmed 0x8001,0x0007,acc1set_fr_iimmed 0xffff,0xffff,fr7 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr8cmmachu fr7,fr8,acc0,cc5,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 1,accg0test_acc_limmed 0x7fff,0x0008,acc0test_accg_immed 1,accg1test_acc_limmed 0x7fff,0x0008,acc1set_accg_immed 0xff,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0xff,accg1set_acc_immed 0xffffffff,acc1set_fr_iimmed 1,1,fr7set_fr_iimmed 1,1,fr8cmmachu fr7,fr8,acc0,cc5,0test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xffff,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xffff,acc1set_fr_iimmed 0xffff,0x0000,fr7set_fr_iimmed 0xffff,0xffff,fr8cmmachu fr7,fr8,acc0,cc5,0test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xffff,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xffff,acc1set_spr_immed 0,msr0set_accg_immed 0x00000011,accg0set_acc_immed 0x11111111,acc0set_accg_immed 0x00000022,accg1set_acc_immed 0x22222222,acc1set_fr_iimmed 3,2,fr7 ; multiply small numbersset_fr_iimmed 2,3,fr8cmmachu fr7,fr8,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 1,2,fr7 ; multiply by 1set_fr_iimmed 2,1,fr8cmmachu fr7,fr8,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0,2,fr7 ; multiply by 0set_fr_iimmed 2,0,fr8cmmachu fr7,fr8,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x3fff,2,fr7 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr8cmmachu fr7,fr8,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x4000,2,fr7 ; 16 bit resultset_fr_iimmed 2,0x4000,fr8cmmachu fr7,fr8,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x8000,2,fr7 ; 17 bit resultset_fr_iimmed 2,0x8000,fr8cmmachu fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr8cmmachu fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x8000,0x8000,fr7 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr8cmmachu fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0xffff,0xffff,fr7 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr8cmmachu fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_accg_immed 0xff,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0xff,accg1set_acc_immed 0xffffffff,acc1set_fr_iimmed 1,1,fr7set_fr_iimmed 1,1,fr8cmmachu fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1set_fr_iimmed 0xffff,0x0000,fr7set_fr_iimmed 0xffff,0xffff,fr8cmmachu fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1set_spr_immed 0,msr0set_accg_immed 0x00000011,accg0set_acc_immed 0x11111111,acc0set_accg_immed 0x00000022,accg1set_acc_immed 0x22222222,acc1set_fr_iimmed 3,2,fr7 ; multiply small numbersset_fr_iimmed 2,3,fr8cmmachu fr7,fr8,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 1,2,fr7 ; multiply by 1set_fr_iimmed 2,1,fr8cmmachu fr7,fr8,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0,2,fr7 ; multiply by 0set_fr_iimmed 2,0,fr8cmmachu fr7,fr8,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x3fff,2,fr7 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr8cmmachu fr7,fr8,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x4000,2,fr7 ; 16 bit resultset_fr_iimmed 2,0x4000,fr8cmmachu fr7,fr8,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x8000,2,fr7 ; 17 bit resultset_fr_iimmed 2,0x8000,fr8cmmachu fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr8cmmachu fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x8000,0x8000,fr7 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr8cmmachu fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0xffff,0xffff,fr7 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr8cmmachu fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_accg_immed 0xff,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0xff,accg1set_acc_immed 0xffffffff,acc1set_fr_iimmed 1,1,fr7set_fr_iimmed 1,1,fr8cmmachu fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1set_fr_iimmed 0xffff,0x0000,fr7set_fr_iimmed 0xffff,0xffff,fr8cmmachu fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1set_spr_immed 0,msr0set_accg_immed 0x00000011,accg0set_acc_immed 0x11111111,acc0set_accg_immed 0x00000022,accg1set_acc_immed 0x22222222,acc1set_fr_iimmed 3,2,fr7 ; multiply small numbersset_fr_iimmed 2,3,fr8cmmachu fr7,fr8,acc0,cc2,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 1,2,fr7 ; multiply by 1set_fr_iimmed 2,1,fr8cmmachu fr7,fr8,acc0,cc2,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0,2,fr7 ; multiply by 0set_fr_iimmed 2,0,fr8cmmachu fr7,fr8,acc0,cc2,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x3fff,2,fr7 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr8cmmachu fr7,fr8,acc0,cc2,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x4000,2,fr7 ; 16 bit resultset_fr_iimmed 2,0x4000,fr8cmmachu fr7,fr8,acc0,cc2,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x8000,2,fr7 ; 17 bit resultset_fr_iimmed 2,0x8000,fr8cmmachu fr7,fr8,acc0,cc6,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr8cmmachu fr7,fr8,acc0,cc6,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x8000,0x8000,fr7 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr8cmmachu fr7,fr8,acc0,cc6,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0xffff,0xffff,fr7 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr8cmmachu fr7,fr8,acc0,cc6,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_accg_immed 0xff,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0xff,accg1set_acc_immed 0xffffffff,acc1set_fr_iimmed 1,1,fr7set_fr_iimmed 1,1,fr8cmmachu fr7,fr8,acc0,cc6,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1set_fr_iimmed 0xffff,0x0000,fr7set_fr_iimmed 0xffff,0xffff,fr8cmmachu fr7,fr8,acc0,cc6,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1;set_spr_immed 0,msr0set_accg_immed 0x00000011,accg0set_acc_immed 0x11111111,acc0set_accg_immed 0x00000022,accg1set_acc_immed 0x22222222,acc1set_fr_iimmed 3,2,fr7 ; multiply small numbersset_fr_iimmed 2,3,fr8cmmachu fr7,fr8,acc0,cc3,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 1,2,fr7 ; multiply by 1set_fr_iimmed 2,1,fr8cmmachu fr7,fr8,acc0,cc3,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0,2,fr7 ; multiply by 0set_fr_iimmed 2,0,fr8cmmachu fr7,fr8,acc0,cc3,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x3fff,2,fr7 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr8cmmachu fr7,fr8,acc0,cc3,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x4000,2,fr7 ; 16 bit resultset_fr_iimmed 2,0x4000,fr8cmmachu fr7,fr8,acc0,cc3,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x8000,2,fr7 ; 17 bit resultset_fr_iimmed 2,0x8000,fr8cmmachu fr7,fr8,acc0,cc7,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr8cmmachu fr7,fr8,acc0,cc7,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0x8000,0x8000,fr7 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr8cmmachu fr7,fr8,acc0,cc7,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_fr_iimmed 0xffff,0xffff,fr7 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr8cmmachu fr7,fr8,acc0,cc7,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1set_accg_immed 0xff,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0xff,accg1set_acc_immed 0xffffffff,acc1set_fr_iimmed 1,1,fr7set_fr_iimmed 1,1,fr8cmmachu fr7,fr8,acc0,cc7,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1set_fr_iimmed 0xffff,0x0000,fr7set_fr_iimmed 0xffff,0xffff,fr8cmmachu fr7,fr8,acc0,cc7,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1pass