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# FRV testcase for dcpl GRi,GRj,lock
# mach: all

        .include "../testutils.inc"

        start

        .global dcpl
dcpl:
        or_spr_immed    0xc8000000,hsr0 ; caches enabled -- copy-back mode

        ; preload and lock all the lines in set 0 of the data cache
        set_gr_immed    0x70000,gr10
        dcpl            gr10,gr0,1
        set_mem_immed   0x11111111,gr10
        test_mem_immed  0x11111111,gr10

        inc_gr_immed    0x2000,gr10
        set_gr_immed    1,gr11
        dcpl            gr10,gr11,1
        set_mem_immed   0x22222222,gr10
        test_mem_immed  0x22222222,gr10

        inc_gr_immed    0x2000,gr10
        set_gr_immed    63,gr11
        dcpl            gr10,gr11,1
        set_mem_immed   0x33333333,gr10
        test_mem_immed  0x33333333,gr10

        inc_gr_immed    0x2000,gr10
        set_gr_immed    64,gr11
        dcpl            gr10,gr11,1
        set_mem_immed   0x44444444,gr10
        test_mem_immed  0x44444444,gr10

        ; Now write to another address which should be in the same set
        ; the write should go through to memory, since all the lines in the
        ; set are locked
        inc_gr_immed    0x2000,gr10
        set_mem_immed   0xdeadbeef,gr10
        test_mem_immed  0xdeadbeef,gr10

        ; Invalidate the data cache. Only the last value stored should have made
        ; it through to memory
        set_gr_immed    0x70000,gr10
        invalidate_data_cache   gr10
        test_mem_immed  0,gr10

        inc_gr_immed    0x2000,gr10
        invalidate_data_cache   gr10
        test_mem_immed  0,gr10

        inc_gr_immed    0x2000,gr10
        invalidate_data_cache   gr10
        test_mem_immed  0,gr10

        inc_gr_immed    0x2000,gr10
        invalidate_data_cache   gr10
        test_mem_immed  0,gr10

        inc_gr_immed    0x2000,gr10
        invalidate_data_cache   gr10
        test_mem_immed  0xdeadbeef,gr10

        pass