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# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
# mach: fr500
# sim(fr500): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010
        .include "testutils.inc"

        start

        .global dsr
dsr:
        and_spr_immed   -4081,tbr               ; clear tbr.tt
        set_gr_spr      tbr,gr17
        inc_gr_immed    0x140,gr17              ; address of exception handler
        set_bctrlr_0_0  gr17
        set_spr_immed   128,lcr
        set_psr_et      1

        set_spr_addr    ok0,lr
        set_gr_immed    0,gr16

        set_gr_immed    0xdeadbeef,gr15
        set_gr_addr     0xfeff0600,gr17
bad1:   sti             gr15,@(gr17,0)          ; cause interrupt
        test_gr_immed   1,gr16

        set_gr_immed    0xbeefdead,gr15
        set_gr_addr     0xfeff7ffc,gr17
bad2:   sti             gr15,@(gr17,0)          ; cause interrupt
        test_gr_immed   2,gr16

        set_gr_immed    0xbeefbeef,gr15
        set_gr_addr     0xfe800000,gr17
bad3:   sti             gr15,@(gr17,0)          ; cause interrupt
        test_gr_immed   3,gr16

        set_gr_immed    0xdeaddead,gr15
        set_gr_addr     0xfefefffc,gr17
bad4:   sti             gr15,@(gr17,0)          ; cause interrupt
        test_gr_immed   4,gr16

        sti             gr0,@(sp,0)             ; no interrupt
        test_gr_immed   4,gr16

        pass
ok0:
        ; check interrupts
        test_spr_immed  0x4000,esfr1            ; esr14 is active
        test_spr_bits   0x0001,0,0x1,esr14      ; esr14 is valid
        test_spr_bits   0x003e,1,0x0,esr14      ; esr14.ec is set
        test_spr_bits   0x0800,11,0x0,esr14     ; esr14.eav is not set

        addi            gr16,1,gr16
        rett            0
        fail