Subversion Repositories sdcard_mass_storage_controller

<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>versatile_fifo_dptam_dw</name><vendor/><library/><version/><fileSets><fileSet fileSetId="ANY_SYNTHESIS_FILESET"><file fileid="0"><name>versatile_fifo_dptam_dw_syn.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="SYNPLIFY_SYNTHESIS_FILESET"><file fileid="1"><name>versatile_fifo_dptam_dw_syn.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="PRECISION_SYNTHESIS_FILESET"><file fileid="2"><name>versatile_fifo_dptam_dw_syn.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="ANY_HDL_SIMULATION_FILESET"><file fileid="3"><name>versatile_fifo_dptam_dw_sim.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="DESIGNER_FILESET"><file fileid="4"><name>versatile_fifo_dptam_dw.cdb</name><userFileType>CDB</userFileType></file></fileSet><fileSet fileSetId="OTHER_FILESET"><file fileid="5"><name>header_report.log</name><userFileType>LOG</userFileType></file><file fileid="6"><name>compile_report.log</name><userFileType>LOG</userFileType></file><file fileid="7"><name>global_report.log</name><userFileType>LOG</userFileType></file><file fileid="8"><name>interface_report.log</name><userFileType>LOG</userFileType></file><file fileid="9"><name>datasheet_report.log</name><userFileType>LOG</userFileType></file><file fileid="10"><name>versatile_fifo_dptam_dw_usedLocations.pdc</name><userFileType>BLOCK_PDC</userFileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>ANY_SYNTHESIS_FILESET</fileSetRef><name>SYNTHESIS</name></view><view><fileSetRef>SYNPLIFY_SYNTHESIS_FILESET</fileSetRef><fileSetRef>PRECISION_SYNTHESIS_FILESET</fileSetRef><fileSetRef>DESIGNER_FILESET</fileSetRef><fileSetRef>OTHER_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>ANY_HDL_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view></views></hwModel><vendorExtension><design><hdltype>VERILOG</hdltype><device die="A3P1000" family="ProASIC3"/></design></vendorExtension><vendorExtension><type>Block</type></vendorExtension><model><signals><signal><name>d_a</name><direction>in</direction><left>7</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>q_a</name><direction>out</direction><left>7</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>adr_a</name><direction>in</direction><left>10</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>we_a</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>clk_a</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>q_b</name><direction>out</direction><left>7</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>adr_b</name><direction>in</direction><left>10</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>d_b</name><direction>in</direction><left>7</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>we_b</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>clk_b</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>