URL
https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk
Subversion Repositories single-14-segment-display-driver-w-decoder
[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1_synplify.lpf] - Rev 5
Go to most recent revision | Compare with Previous | Blame | View Log
#
# Logical Preferences generated for Lattice by Synplify maplat, Build 1498R.
#
# Period Constraints
#FREQUENCY PORT "clk" 1220.4 MHz;
# Output Constraints
# Input Constraints
# Point-to-point Delay Constraints
# Block Path Constraints
BLOCK ASYNCPATHS;
# End of generated Logical Preferences.
Go to most recent revision | Compare with Previous | Blame | View Log