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<?xml version="1.0" encoding="UTF-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
//                                                                        //
//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
//   the original copyright notice and the associated disclaimer.         //
//                                                                        //
//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
//   either version 2.1 of the License, or (at your option) any           //
//   later version.                                                       //
//                                                                        //
//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
//                                                                        //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
-->
<ipxact:design 
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>Mos6502</ipxact:library>
<ipxact:name>T6502</ipxact:name>
<ipxact:version>ctrl.design</ipxact:version>  


<ipxact:vendorExtensions>
<socgen:nodes>

<socgen:node>
<ipxact:name>pg00_ram_l_wr</ipxact:name>
<ipxact:typeName>wire</ipxact:typeName>
</socgen:node>


<socgen:node>
<ipxact:name>pg00_ram_h_wr</ipxact:name>
<ipxact:typeName>wire</ipxact:typeName>
</socgen:node>



<socgen:node>
<ipxact:name>pg00_ram_rd</ipxact:name>
<ipxact:typeName>wire</ipxact:typeName>
</socgen:node>



</socgen:nodes>
</ipxact:vendorExtensions>


<ipxact:adHocConnections>


    <ipxact:adHocConnection>
      <ipxact:name>clk</ipxact:name>
      <ipxact:externalPortReference portRef="clk"/>
      <ipxact:internalPortReference componentRef="pg00_ram_l" portRef="clk"/>
      <ipxact:internalPortReference componentRef="pg00_ram_h" portRef="clk"/>
    </ipxact:adHocConnection>



    <ipxact:adHocConnection  tiedValue="1'b1">
      <ipxact:internalPortReference componentRef="pg00_ram_l" portRef="cs"/>
      <ipxact:internalPortReference componentRef="pg00_ram_h" portRef="cs"/>
    </ipxact:adHocConnection>



    <ipxact:adHocConnection>
      <ipxact:name>pg0_add</ipxact:name>
      <ipxact:externalPortReference portRef="pg0_add"  left="7"   right="1"      />
      <ipxact:internalPortReference componentRef="pg00_ram_l" portRef="raddr"/>
      <ipxact:internalPortReference componentRef="pg00_ram_h" portRef="raddr"/>
      <ipxact:internalPortReference componentRef="pg00_ram_l" portRef="waddr"/>
      <ipxact:internalPortReference componentRef="pg00_ram_h" portRef="waddr"/>
    </ipxact:adHocConnection>






    <ipxact:adHocConnection>
      <ipxact:name>pg00_ram_rd</ipxact:name>
      <ipxact:externalPortReference portRef="pg0_ram_rd"/>
      <ipxact:internalPortReference componentRef="pg00_ram_l" portRef="rd"/>
      <ipxact:internalPortReference componentRef="pg00_ram_h" portRef="rd"/>
    </ipxact:adHocConnection>



    <ipxact:adHocConnection>
      <ipxact:name>mem_rdata</ipxact:name>
      <ipxact:externalPortReference portRef="mem_rdata"  left="7"   right="0"      />
      <ipxact:internalPortReference componentRef="pg00_ram_l" portRef="rdata"/>
    </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>mem_rdata</ipxact:name>
      <ipxact:externalPortReference portRef="mem_rdata"  left="15"   right="8"      />
      <ipxact:internalPortReference componentRef="pg00_ram_h" portRef="rdata"/>
    </ipxact:adHocConnection>



    <ipxact:adHocConnection>
      <ipxact:name>mem_wdata</ipxact:name>
      <ipxact:externalPortReference portRef="mem_rdata"  left="7"   right="0"      />
      <ipxact:internalPortReference componentRef="pg00_ram_l" portRef="wdata"/>
    </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>mem_wdata</ipxact:name>
      <ipxact:externalPortReference portRef="mem_rdata"  left="15"   right="8"      />
      <ipxact:internalPortReference componentRef="pg00_ram_h" portRef="wdata"/>
    </ipxact:adHocConnection>








    <ipxact:adHocConnection>
      <ipxact:name>pg00_ram_l_wr</ipxact:name>
      <ipxact:externalPortReference portRef="pg0_ram_l_wr"/>
      <ipxact:internalPortReference componentRef="pg00_ram_l" portRef="wr"/>
    </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>pg00_ram_h_wr</ipxact:name>
      <ipxact:externalPortReference portRef="pg0_ram_h_wr"/>
      <ipxact:internalPortReference componentRef="pg00_ram_h" portRef="wr"/>
    </ipxact:adHocConnection>




</ipxact:adHocConnections>



<ipxact:componentInstances>



<ipxact:componentInstance>
<ipxact:instanceName>pg00_ram_l</ipxact:instanceName>
<ipxact:componentRef vendor="opencores.org" library="cde" name="sram" version="dp"/>
<ipxact:configurableElementValues>
<ipxact:configurableElementValue referenceId="WIDTH">PG0_WIDTH</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="ADDR">PG0_ADDR</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="WORDS">PG0_WORDS</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="WRITETHRU">PG0_WRITETHRU</ipxact:configurableElementValue>
</ipxact:configurableElementValues>
</ipxact:componentInstance>




<ipxact:componentInstance>
<ipxact:instanceName>pg00_ram_h</ipxact:instanceName>
<ipxact:componentRef vendor="opencores.org" library="cde" name="sram" version="dp"/>
<ipxact:configurableElementValues>
<ipxact:configurableElementValue referenceId="WIDTH">PG0_WIDTH</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="ADDR">PG0_ADDR</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="WORDS">PG0_WORDS</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="WRITETHRU">PG0_WRITETHRU</ipxact:configurableElementValue>
</ipxact:configurableElementValues>
</ipxact:componentInstance>


</ipxact:componentInstances>











</ipxact:design>