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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_wb_cpu0_jsp.xml] - Rev 133
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<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Author : John Eaton Ouabache Designworks //
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>adv_debug_sys</spirit:library>
<spirit:name>adv_dbg_if</spirit:name>
<spirit:version>wb_cpu0_jsp</spirit:version> <spirit:configuration>default</spirit:configuration>
<spirit:componentGenerators>
<spirit:componentGenerator>
<spirit:name>elab_verilog</spirit:name>
<spirit:phase>102.1</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>io_ports</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>wb_cpu0_jsp</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
</spirit:componentGenerators>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/wb_cpu0_jsp_defines.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>include</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/adbg_or1k_defines.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>include</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/adbg_wb_defines.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>include</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/adbg_top.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName>crc32</spirit:logicalName>
<spirit:name>../verilog/adbg_crc32.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName>jsp_biu</spirit:logicalName>
<spirit:name>../verilog/adbg_jsp_biu.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName>jsp_module</spirit:logicalName>
<spirit:name>../verilog/adbg_jsp_module.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName>or1k_biu</spirit:logicalName>
<spirit:name>../verilog/adbg_or1k_biu.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName>or1k_module</spirit:logicalName>
<spirit:name>../verilog/adbg_or1k_module.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName>or1k_status_reg</spirit:logicalName>
<spirit:name>../verilog/adbg_or1k_status_reg.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName>wb_biu</spirit:logicalName>
<spirit:name>../verilog/adbg_wb_biu.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName>wb_module</spirit:logicalName>
<spirit:name>../verilog/adbg_wb_module.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName>bytefifo</spirit:logicalName>
<spirit:name>../verilog/adbg_bytefifo.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName>syncflop</spirit:logicalName>
<spirit:name>../verilog/adbg_syncflop.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName>syncreg</spirit:logicalName>
<spirit:name>../verilog/adbg_syncreg.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>module</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>jtag</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="adv_debug_sys"
spirit:name="adv_dbg_if"
spirit:version="jtag_i"/>
</spirit:vendorExtensions>
</spirit:view>
<spirit:view>
<spirit:name>cpu0</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="adv_debug_sys"
spirit:name="adv_dbg_if"
spirit:version="cpu0_i"/>
</spirit:vendorExtensions>
</spirit:view>
<spirit:view>
<spirit:name>wb</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="adv_debug_sys"
spirit:name="adv_dbg_if"
spirit:version="wb_i"/>
</spirit:vendorExtensions>
</spirit:view>
<spirit:view>
<spirit:name>jsp</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="adv_debug_sys"
spirit:name="adv_dbg_if"
spirit:version="jsp_i"/>
</spirit:vendorExtensions>
</spirit:view>
<spirit:view>
<spirit:name>verilog</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="verilog"/>
</spirit:vendorExtensions>
</spirit:view>
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>doc</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="documentation"/>
</spirit:vendorExtensions>
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port><spirit:name>int_o</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>biu_wr_strobe</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>jsp_data_out</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
</spirit:component>
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