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<?xml version="1.0" encoding="utf-8"?>
<!--
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>adv_debug_sys</spirit:library>
<spirit:name>adv_dbg_if</spirit:name>
<spirit:version>jfifo_sync_tb</spirit:version>
<spirit:componentGenerators>
<spirit:componentGenerator>
<spirit:name>gen_verilog</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>adv_dbg_if_jfifo_sync_tb</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
</spirit:componentGenerators>
<spirit:model>
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>JTAG_MODEL_DIVCNT</spirit:name> <spirit:value>4'h4</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>JTAG_MODEL_SIZE</spirit:name> <spirit:value>4</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>wb_addr_width</spirit:name> <spirit:value>32</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>wb_data_width</spirit:name> <spirit:value>32</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
<spirit:views>
<spirit:view>
<spirit:name>Params</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="adv_debug_sys"
spirit:name="adv_dbg_if"
spirit:version="jfifo_dut.params"/>
</spirit:vendorExtensions>
</spirit:view>
<spirit:view>
<spirit:name>Bfm</spirit:name>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="adv_debug_sys"
spirit:name="adv_dbg_if"
spirit:version="bfm.design"/>
</spirit:view>
<spirit:view>
<spirit:name>Jfifo_Bfm</spirit:name>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="adv_debug_sys"
spirit:name="adv_dbg_if"
spirit:version="jfifo_bfm.design"/>
</spirit:view>
<spirit:view>
<spirit:name>icarus</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="icarus"/>
</spirit:vendorExtensions>
</spirit:view>
<spirit:view>
<spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-common</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>lint</spirit:name><spirit:envIdentifier>:*Lint:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-lint</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-common</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.jfifo_sync</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>fragment</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/adv_dbg_if_jfifo_sync_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/common/adv_dbg_if_jfifo_sync_tb</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
</spirit:component>
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