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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [xml/] [model_master.xml] - Rev 131
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<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Author : John Eaton Ouabache Designworks //
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>wishbone</spirit:library>
<spirit:name>model</spirit:name>
<spirit:version>master</spirit:version> <spirit:configuration>default</spirit:configuration>
<spirit:busInterfaces>
<spirit:busInterface><spirit:name>wb</spirit:name>
<spirit:busType spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wishbone" spirit:version="def"/>
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wishbone" spirit:version="rtl"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort><spirit:name>adr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort><spirit:name>adr</spirit:name>
<spirit:wire><spirit:vector><spirit:left>wb_addr_width-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>wdata</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort><spirit:name>dout</spirit:name>
<spirit:wire><spirit:vector><spirit:left>wb_data_width-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>rdata</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort><spirit:name>din</spirit:name>
<spirit:wire><spirit:vector><spirit:left>wb_data_width-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>sel</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort><spirit:name>sel</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>ack</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort><spirit:name>ack</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>cyc</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort><spirit:name>cyc</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>stb</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort><spirit:name>stb</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>we</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort><spirit:name>we</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:model>
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>dwidth</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>awidth</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
<spirit:ports>
<spirit:port><spirit:name>clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>reset</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>adr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>awidth-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>dout</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>dwidth</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>cyc</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>stb</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>we</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>sel</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>dwidth/8-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>din</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>dwidth-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>ack</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>err</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>rty</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
</spirit:component>
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