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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [clock_gen/] [rtl/] [verilog/] [clock_gen_syn] - Rev 134

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always@(posedge clk or negedge START)
  if(!START)  FINISH <= 0;
  else        FINISH <= (|STOP) || FINISH;



always@(posedge clk or negedge START)
  if(!START)  FAIL <= 0;
  else        FAIL <= (|BAD);
   

always@(posedge clk or negedge START)
  if(!START)  reset <= 1'b1;
  else        reset <= 1'b0;
  

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