URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [clock_gater] - Rev 134
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wire latch_enable;reg latch_output;assign latch_enable = enable | atg_clk_mode;always @(latch_enable or clk_in)beginif (~clk_in)latch_output = latch_enable;elselatch_output = latch_output;endassign clk_out = latch_output && clk_in;