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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [verilog/] [sync_with_reset] - Rev 134

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reg [WIDTH - 1:0] sync_data [DEPTH:0]; 


always @(*)
  begin
    sync_data[0] = data_in;
  end
  


integer i;
always @(posedge clk or negedge reset_n) 
  if (~reset_n)
     begin 
     for (i = 1 ; i <= DEPTH ; i = i + 1)      sync_data[i] <= RST_VAL;           
     end 

  else
     begin  
     for (i = 1 ; i <= DEPTH ; i = i + 1)      sync_data[i] <= sync_data[i-1];      
     end
   
assign data_out = sync_data[DEPTH];

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