OpenCores
URL https://opencores.org/ocsvn/t400/t400/trunk

Subversion Repositories t400

[/] [t400/] [trunk/] [syn/] [t421/] [ep1c12/] [t421.qsf] - Rev 176

Compare with Previous | Blame | View Log

set_global_assignment -name TOP_LEVEL_ENTITY t421
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#               t421_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#               assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:20:14  April 27, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 7.0
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_opt_pack-p.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_clkgen.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_reset.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_pack-p.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_pmem_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_dmem_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_comp_pack-p.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_mnemonic_pack-p.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_decoder.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_skip.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_alu.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_stack.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_io_pack-p.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_io_l.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_io_d.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_io_g.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_io_in.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_sio.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_timer.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_core.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/tech/generic/generic_ram_ena.vhd
set_global_assignment -name VHDL_FILE rom_t42x.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t420_rom-e.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t420_rom-struct-a.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/tech/cyclone/t400_por.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_core_comp_pack-p.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/tech/t400_tech_comp_pack-p.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t420_notri.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t400_system_comp_pack-p.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t421.vhd

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name VHDL_INPUT_VERSION VHDL87

set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C12Q240C8
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name FMAX_REQUIREMENT "4 MHz" -section_id ck_i
set_instance_assignment -name CLOCK_SETTINGS ck_i -to ck_i
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE AREA

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.