Subversion Repositories t6507lp

    // --------------------------------- //
    //  Includes & Category Definitions  //
    // --------------------------------- //

category ALL "This category consists of all the categories in HAL" default_on
{
  ALL_BEHAVIORAL        // Category of all the Behavioral level checks
  ALL_RTL       // Category of all the RTL level checks
  ALL_NETLIST   // Category of all the Netlist level checks
  ALL_TOOL      // HAL usage errors
  ALL_SYSTEMC   // SystemC(r) specific checks
}

category ALL_BEHAVIORAL "Category of all the Behavioral level checks" default_on
{
  BEH_CODINGSTYLE_VHDL          // Behavioral level coding style checks
}

category ALL_RTL "Category of all the RTL level checks" default_on
{
  RTL_NAMING    // Category of all the RTL Naming checks
  RTL_FILEFORMAT        // Category of all the RTL File format checks
  RTL_CODECOMMENT       // Category of all the RTL Code comment checks
  RTL_CODINGSTYLE       // Category of all the RTL coding style checks
  RTL_SIMSYNTH          // Category of pre and post-synthesis simulation mismatch checks
  RTL_SYNTH     // Category of all the synthesizability checks
  RTL_SIMRACE   // Category of all the simulation race condition checks
  DFT   // Verilog and VHDL DFT checks
  FSM   // Verilog and VHDL, FSM coding style checks
  STRUCTURAL    // Verilog/VHDL structural checks
  CLOCKDOMAIN   // Verilog/VHDL clock domain checks
  PALLADIUM     // Category of all the checks to qualify design to run on Palladium
  RMM   // All checks complying to Reuse Methodology Manual
  LOW_POWER     // All checks related to low power design
}

category ALL_NETLIST "Category of all the Netlist level checks" default_on
{
  DFT   // Verilog and VHDL DFT checks
  STRUCTURAL    // Verilog/VHDL structural checks
  CLOCKDOMAIN   // Verilog/VHDL clock domain checks
  SCANCHAIN     // Verilog/VHDL Netlist level scan chain checks
}

category RTL_NAMING "Category of all the RTL Naming checks" default_off
{
  RTL_NAMING_VERILOG    // Verilog only Naming checks
  RTL_NAMING_VHDL       // VHDL only Naming checks
  RTL_NAMING_MIXED      // Naming checks for Verilog and VHDL
  RTL_NAMING_ASSERTIONS         // SystemVerilog Assertion only Naming checks
}

category RTL_FILEFORMAT "Category of all the RTL File format checks" default_on
{
  RTL_FILEFORMAT_VERILOG        // Verilog only File format checks
  RTL_FILEFORMAT_VHDL   // VHDL only File format checks
  RTL_FILEFORMAT_MIXED          //  File format checks for Verilog and VHDL
}

category RTL_CODECOMMENT "Category of all the RTL Code comment checks" default_off
{
  RTL_CODECOMMENT_VERILOG       // Verilog only Code comment checks
  RTL_CODECOMMENT_MIXED         // Code comment checks for Verilog and VHDL
}

category RTL_CODINGSTYLE "Category of all the RTL coding style checks" default_on
{
  RTL_CODINGSTYLE_VERILOG       // Verilog only coding style checks
  RTL_CODINGSTYLE_VHDL          // VHDL only coding style checks
  RTL_CODINGSTYLE_MIXED         // coding style checks for Verilog and VHDL
  RTL_CODINGSTYLE_ASSERTIONS    // coding style checks for Assertions
}

category RTL_SIMRACE "Category of all the simulation race condition checks" default_on
{
  RTL_SIMRACE_VERILOG   // Verilog only simulation race condition checks
}

category RTL_SIMSYNTH "Category of pre and post-synthesis simulation mismatch checks" default_on
{
  RTL_SIMSYNTH_VERILOG          // Verilog only pre and post-synthesis simulation mismatch checks
  RTL_SIMSYNTH_MIXED    // Verilog/VHDL pre and post-synthesis simulation mismatch checks
}

category RTL_SYNTH "Category of all the synthesizability checks" default_on synth_only
{
  RTL_SYNTH_VERILOG     // Verilog only synthesizability checks
  RTL_SYNTH_VHDL        // VHDL only synthesizability checks
  RTL_SYNTH_MIXED       // Verilog and VHDL  synthesizability checks
}

category ALL_SYSTEMC "SystemC(r) specific checks" default_on
{
  BDSGIT  // Null value passed for the name argument of the SystemC %s '%s' 
  WTINMT  // Wait function called by the SystemC method '%s' of class '%s' 
  STINMT  // Function 'sc_start' called by the SystemC method '%s' of class '%s' 
  STINTD  // Function 'sc_start' called by the SystemC thread '%s' of class '%s' 
  CYINMT  // Function 'sc_cycle' called by the SystemC method '%s' of class '%s' 
  CYINTD  // Function 'sc_cycle' called by the SystemC thread '%s' of class '%s' 
  ITINMT  // Function 'sc_initialize' called by the SystemC method '%s' of class '%s' 
  ITINTD  // Function 'sc_initialize' called by the SystemC thread '%s' of class '%s' 
  BDMDCT  // Module name argument not declared in constructor '%s' as 'sc_module_name' 
  BDOBNM  // Bad value '%s' passed for the name argument of SystemC %s, '%s' 
  DFOBNM  // The value '%s' passed for the name argument of SystemC %s, '%s', is different from the field name 
  OBNONM  // The SystemC %s '%s' is initialized with no name 
  OBNOIT  // The SystemC %s '%s' is not explicitly named in the initializaton list of the module constructor 
  DFVWNM  // The value '%s' passed for the name argument of SystemC viewable object '%s' is different from the name of the field that it references: '%s' 
  OBISLV  // SystemC object '%s' is declared as a local variable 
  OBISGV  // SystemC object '%s' is declared as a global variable 
  OBISFP  // SystemC object '%s' is declared as a formal parameter of a function 
  PIINCT  // A port interface method called in the constructor of SystemC module '%s' 
  WTINCT  // Wait function called by the constructor of SystemC module '%s' 
  WTINMN  // Wait function called by the sc_main function 
  WTINUP  // Wait function called by the update method of SystemC primitive channel, '%s' 
  RUINUP  // request_update function called by the update method of SystemC primitive channel, '%s' 
  EFINWT  // A function call, returning sc_event_finder&, passed as an argument to the wait function 
  CYISDP  // The function sc_cycle is deprecated in SystemC 2.1. Use sc_start instead 
  BDSPRV  // Bad argument passed, for the return value of the spawned process, in the sc_spawn function call 
  SGPIRW  // %s->%s() called instead of %s.%s(). The latter is more efficient 
  MDINNM  // The SystemC module, '%s', is declared in the namespace '%s' 
  IFNOVB  // The sc_interface class is not a virtual base class of the SystemC interface '%s' 
  BDPORT  // The SystemC port, '%s', is passing an invalid template argument to base class, sc_port 
  OLCLDL  // Old style declaration found for SystemC clock '%s' 
  BDCLPR  // The SystemC clock, '%s', is initialized with a bad value for clock period. It should be > 0 
  BDCLDC  // The SystemC clock, '%s', is initialized with a bad value for duty cycle. It should be between 0 and 1 
  MDINLS  // The SystemC module, '%s', is declared in the inner (local) scope of a class or function 
  BDPRNM  // Bad value '%s' passed for the name argument of process created using sc_spawn 
  PRNONM  // The process created using sc_spawn was not initialized with a name 
  NOBSCN  // The macro SCV_BASE_CONSTRAINT(%s) not called in the constructor of constraint class '%s' 
  UCONMF  // The method use_constraint called on the member field '%s' of constraint class '%s' 
  BDHCAG  // The argument to method sc_hdl_task_handle::call_task has an unsupported type: '%s' 
  HCINCT  // The method sc_hdl_task_handle::%s called in the constructor of SystemC module '%s' 
  CBNOVB  // The scv_constraint_base class is not a virtual base class of constraint '%s' 
  BDRFFP  // The formal parameter #%d of function '%s' has an unsupported type: '%s' 
  PBINPR  // Port binding in SystemC Process '%s' of class '%s' is not allowed 
  BWDIFF  // Assigning %s to %s: bit widths are different 
  BDINAG  // Only the base class can be passed as an argument to macro, SCV_INIT 
  BDEXCT  // Only the base class can be passed as an argument to macro, SCV_EXTENSIONS_BASE_CLASS 
  STRSUB  // sc_string is typedef'd to std::string. The call to std::string::substr has different semantics than the call to sc_string::substr in previous versions of SystemC 
}

category BEH_CODINGSTYLE_VHDL "Behavioral level coding style checks" default_on
{
  WNBFLK {level="1"} // Port '%s' should not be of mode buffer or linkage 
  SYNCSL {level="1"} // The sensitivity list of a sequential process does not contain an asynchronous reset 
  BEHINI {level="2"} // A behavioral variable/signal '%s' is not initialized in its declaration 
  SUBTNM {level="2"} // Subtype name '%s' does not contain the type name '%s' 
  ENTDCL {level="2"} // A VHDL entity should only consist of generic and port interface lists 
  UNITNM {level="2"} // VHDL design-unit name '%s' is missing on the end line 
  SUBPNM {level="2"} // VHDL %s name '%s' is missing on the end line 
  NOLABL {level="2"} // Process label '%s' is missing as a closing label 
  ALOWID {level="2"} // Signal/variable name '%s' does not follow the active-low naming convention 
  MAXPRT {level="3"} // Entity '%s' must not have more than %d ports 
  PDFPKG {level="3"} // The standard/IEEE package '%s' should not be used 
  MLITNU {level="3"} // The enumeration type '%s' should not contain more than %d literals 
  DESULN {level="3"} // The length of design-unit '%s' should not exceed %d lines 
  FENAME {level="2"} // Identifier '%s' updated on negative edge of clock should have '_f' as suffix 
  USRATN {level="3"} // User-defined attribute '%s' is being used in architecture '%s' 
}

category RTL_NAMING_VERILOG "Verilog only Naming checks" default_off
{
  MODLNM {level="4"} // Module name '%s' does not follow the naming convention 
  SVIFNM {level="4"} // SystemVerilog interface name '%s' does not follow the recommended naming convention 
  INSTNM {level="4"} // Instance name '%s' does not follow the naming convention 
  BLKLNM {level="4"} // Begin/end block name '%s' does not follow the naming convention 
  FUNCNM {level="4"} // Function name '%s' does not follow the naming convention 
  TASKNM {level="4"} // Task name '%s' does not follow the naming convention 
  PARMNM {level="4"} // Parameter name '%s' does not follow the naming convention 
  INTGNM {level="4"} // Integer variable name '%s' does not follow the naming convention 
  REALNM {level="4"} // Real variable name '%s' does not follow the naming convention 
  MEMRNM {level="4"} // Memory name '%s' does not follow the naming convention 
  WIRENM {level="4"} // Wire name '%s' does not follow the naming convention 
  REGRNM {level="4"} // Register name '%s' does not follow the naming convention 
  VLFLNM {level="4"} // File name '%s' does not follow the recommended naming convention%s 
}

category RTL_NAMING_ASSERTIONS "SystemVerilog Assertion only Naming checks" default_off
{
  LOCVNM {level="4"} // Local variable '%s' in %s does not follow the recommended naming convention 
  ASTMNM {level="4"} // Assert statement '%s' does not follow the recommended naming convention 
  COVRNM {level="4"} // Cover statement '%s' does not follow the recommended naming convention 
  ASUMNM {level="4"} // Assume statement '%s' does not follow the recommended naming convention 
  PROPNM {level="4"} // Property '%s' does not follow the recommended naming convention 
  SEQNNM {level="4"} // Sequence '%s' does not follow the recommended naming convention 
}

category RTL_NAMING_VHDL "VHDL only Naming checks" default_off
{
  ARCHNM {level="4"} // Architecture name '%s' does not follow the naming convention 
  ENTYNM {level="4"} // Entity name '%s' does not follow the naming convention 
  PCKGNM {level="4"} // Package name '%s' does not follow the naming convention 
  CMPPKG {level="4"} // Package name %s does not follow the recommended naming convention 
  SUBRNM {level="4"} // Subprogram name '%s' does not follow the naming convention 
  ACCSNM {level="4"} // Access-type name '%s' does not follow the naming convention 
  CNSTNM {level="4"} // Constant name '%s' does not follow the naming convention 
  FILENM {level="4"} // File name '%s' does not follow the naming convention 
  LIBRNM {level="4"} // Library name '%s' does not follow the naming convention 
  SIGLNM {level="4"} // Signal name '%s' does not follow the naming convention 
  VARLNM {level="4"} // Variable name '%s' does not follow the naming convention 
  CONFNM {level="4"} // Configuration name '%s' does not follow the recommended naming convention 
  CONFIL {level="4"} // Configuration file name '%s' does not follow the naming convention 
}

category RTL_NAMING_MIXED "Naming checks for Verilog and VHDL" default_off
{
  PORTNM {level="4"} // Port name '%s' does not follow the naming convention 
  TBCHNM {level="4"} // File name '%s' does not follow the recommended testbench naming convention%s 
  OUTPNM {level="4"} // Output port name '%s' does not follow the naming convention 
  INPTNM {level="4"} // Input port name '%s' does not follow the naming convention 
  IOPTNM {level="4"} // Inout port name '%s' does not follow the naming convention 
  CLKSNM {level="4"} // Clock signal name '%s' does not follow the naming convention 
  RSTNAM {level="4"} // Reset signal name '%s' does not follow the recommended naming convention 
  DIFCLK {level="2"} // Clock '%s' is being renamed to '%s' 
  DIFRST {level="2"} // Set/Reset '%s' is being renamed to '%s' 
  RENAME {level="4"} // Signal '%s' renamed as '%s' 
  UCOPNM {level="4"} // Unconnected output signal name '%s' does not follow the recommended naming convention 
  NTACHR {level="4"} // Identifier '%s' contains characters that are not allowed 
  FCNLTR {level="4"} // First character of identifier '%s' is not a letter 
  ESCNTA {level="4"} // Identifier '%s' contains escaped names, which should not be used 
  RGOPNM {level="4"} // Output register name '%s' does not follow the recommended naming convention 
  TESTNM {level="4"} // Test mode signal '%s' does not follow the recommended naming convention 
  HIMPNM {level="4"} // High impedance signal name '%s' does not follow the recommended naming convention 
  STMCNM {level="4"} // State machine's state '%s' does not follow the recommended naming convention 
  LTCHNM {level="4"} // Latch '%s' does not follow the recommended naming convention 
  MULSNO {level="4"} // Signal name '%s' does not follow the multiple suffix naming order 
  DIFSIG {level="4"} // Actual port name '%s' of instance '%s' does not follow the recommended naming convention 
}

category RTL_FILEFORMAT_VERILOG "Verilog only File format checks" default_on
{
  VERREP {level="3"} // Repeated usage of identifier or label name '%s' 
  KEYWOD {level="3"} // VHDL reserved word '%s' used as an identifier or label 
  MULTMF {level="3"} // More than one design-unit definition in file '%s' 
  PRTODR {level="4"} // Port declaration '%s' does not follow the port layout order or/and does not match the port list 
  PRTLYO {level="4"} // Ports declared in module '%s' do not follow the port layout order 
}

category RTL_FILEFORMAT_VHDL "VHDL only File format checks" default_on
{
  CASMIS {level="2"} // VHDL object '%s' has case mismatch between instantiation and declaration 
  COMDIF {level="2"} // VHDL object '%s' has mismatch between component and its entity declaration 
  VHDREP {level="3"} // Repeated usage of identifier or label name '%s' 
  STYSUL {level="3"} // Type std_ulogic used for identifier '%s'. Use std_logic to avoid portability issues 
  STYSUV {level="3"} // Type std_ulogic vector used for identifier '%s'. Use std_logic_vector to avoid portability issues 
  STYBIT {level="3"} // Type bit used for identifier '%s'. Use std_logic to avoid portability issues 
  STYBTV {level="3"} // Type bit_vector used for identifier '%s'. Use std_logic_vector to avoid portability issues 
  GENUSD {level="3"} // Generate statement used. This will create portability issues 
  STYBLK {level="3"} // Block statement used. This will create portability issues 
  MXPROC {level="3"} // The architecture '%s' contains more than %d process statements 
  ONELIB {level="2"} // Single library declaration clause used to declare multiple library names 
  INPPRT {level="4"} // Input port '%s' does not follow the layout convention 
  CLKPRT {level="4"} // Clock port '%s' does not follow the layout convention 
  RSTPRT {level="4"} // Reset port '%s' does not follow the layout convention 
  INOPRT {level="4"} // Inout/Buffer port '%s' does not follow the layout convention 
  ARCHID {level="3"} // Architecture name '%s' does not follow recommended naming convention 
}

category RTL_FILEFORMAT_MIXED " File format checks for Verilog and VHDL" default_on
{
  VERCAS {level="2"} // Identifier, label, instance, or module name '%s' reused with a case difference 
  DIRRNG {level="2"} // Inconsistent ordering of bits in range declarations -- should be all %s ranges 
  KYEDIF {level="2"} // EDIF reserved word '%s' used as an identifier or label 
  NEEDIO {level="2"} // Top-level %s '%s' has no inputs/outputs/inouts 
  IDLENG {level="2"} // Identifier name '%s' is not of appropriate length (%d to %d characters) 
  ALOWNM {level="2"} // Identifier '%s' does not follow the recommended naming convention 
  KVHWOD {level="3"} // Verilog reserved word '%s' used as an identifier or label 
  STYVAL {level="3"} // Numeric value '%d' used for identifier '%s'. Use constants to avoid portability issues 
  SUBPLN {level="3"} // The length of subprogram '%s' should not exceed %d lines 
  SYSVKW {level="3"} // SystemVerilog reserved word '%s' used as an identifier or label 
  AMSKWD {level="3"} // AMS reserved word '%s' used as an identifier or label 
  CTLCHR {level="4"} // HDL source line contains one or more control characters 
  UPCLBL {level="4"} // Label '%s' should be written in uppercase 
  DIFFMN {level="4"} // %s name '%s' differs from file name '%s' 
  NOBLKN {level="4"} // Each block should be labeled with a meaningful name 
  SEPLIN {level="4"} // Use a separate line for each HDL statement 
  LCVARN {level="4"} // %s name '%s' uses uppercase characters 
  UCCONN {level="4"} // Lowercase characters used for identifier '%s'. Use uppercase characters for names of constants and user-defined types 
  NOINSN {level="4"} // Each module/gate/primitive instance should be labeled with a meaningful name 
  FILSUF {level="4"} // The file name '%s' is missing a valid HDL file name extension 
  DECLIN {level="4"} // Use a separate line for each HDL declaration 
  MAXLEN {level="4"} // The HDL source line is %d characters, which exceeds the recommended length of %d characters 
  SIGLEN {level="4"} // Signal name '%s' is not of appropriate length (%d to %d characters) 
}

category RTL_CODECOMMENT_VERILOG "Verilog only Code comment checks" default_off
{
  COMSTY {level="4"} // Do not use '%s' comment style in code 
  COMINS {level="4"} // Instantiated cells should have a comment on the same or preceding line 
  COMDIR {level="4"} // Compiler directive '%s' should have a comment on the same or preceding line 
  COMEND {level="4"} // Verilog end/endcase statement should have a comment on the same line 
  COMLTH {level="4"} // Latch declarations should have a comment on the same or preceding line 
}

category RTL_CODECOMMENT_MIXED "Code comment checks for Verilog and VHDL" default_off
{
  COMBLK {level="4"} // Always/process block should have a comment on the same or preceding line 
  COMIOP {level="4"} // Port declarations should have a comment on the same or preceding line 
  COMDEC {level="4"} // Net/signal declarations should have a comment on the same or preceding line 
  COMGTD {level="4"} // Gated clocks should have a comment on the same or preceding line 
  FHDRFT {level="4"} // File header format does not follow the template 
  SHDRFT {level="4"} // Sub-header format for %s does not follow the template 
}

category RTL_CODINGSTYLE_VERILOG "Verilog only coding style checks" default_on
{
  NBCOMB {level="1"} // Non-blocking assignment encountered in a combinational block 
  IFDDEF {level="1"} // Macro '%s' is defined using `define statement in the same verilog file 
  BLKSQB {level="1"} // Blocking assignment encountered in a sequential block 
  CDEFCV {level="1"} // The case items of the case statement cover all the numerical values of the case expression. The default clause is not required 
  BLNBLK {level="1"} // Signal '%s' is assigned via both blocking and non-blocking assignments 
  EVUNTR {level="1"} // Event variable '%s' is never triggered 
  LOGAND {level="1"} // Bit-wise AND in a conditional expression.  Logical AND may have been intended 
  LOGORP {level="1"} // Bit-wise OR in a conditional expression.  Logical OR may have been intended 
  LOGNEG {level="1"} // Bit-wise negation in a conditional expression.  Logical NOT may have been intended 
  MULOPR {level="1"} // Logical %s operator applied to multi-bit operand %s 
  CDEFNC {level="1"} // Case statement %s 
  INCMPC {level="1"} // Not all cases are covered in the parallel case (%d of possible %d covered) 
  CASEZX {level="1"} // Case item expression contains 'x' for a casez statement (useful only in casex statements) 
  OBMEMI {level="1"} // Memory word '%s[%s]' has an index of size %d, which may reference a memory word, which is outside the defined range of the memory (%d words) 
  DIFRNG {level="1"} // Port '%s' with range (%d to %d) is re-declared with a different range (%d to %d) 
  CONSLC {level="1"} // Module '%s' contains a loop with a constant termination conditional expression 
  OOMCAL {level="1"} // Use of an out-of-module task call to %s 
  INPOUT {level="1"} // Primary input port %s of module %s may be driven inside the module 
  SIZMIS {level="1"} // Port '%s' has size mismatch between module instantiation and declaration 
  PRTSYN {level="1"} // Port '%s' is declared using a mix of VLOG95 and VLOG2001 declaration styles 
  UELASG {level="1"} // Unequal length operand in assignment 
  CONDSZ {level="1"} // Expression in condition does not result in a single bit value 
  OPLVNC {level="1"} // '%s' operation between loop variable '%s' and non constant value '%s' 
  PRMVAL {level="1"} // Bit width not specified for parameter '%s' 
  PRMBSE {level="1"} // Base not specified for parameter '%s' 
  MULCAS {level="1"} // Overlapping case item %s 
  NBFUNC {level="2"} // Non-blocking assignment encountered in function '%s' 
  BADSYS {level="2"} // System task %s in %s %s is ignored 
  RTLNOG {level="2"} // Gate instances are not expected in an RTL design 
  RTLNOP {level="2"} // Primitive instances are not expected in an RTL design 
  RTLINI {level="2"} // A variable/signal '%s' in an RTL description is initialized in its declaration 
  PLIFTN {level="2"} // PLI 1.0 function %s in module '%s' is ignored 
  EMPSTM {level="2"} // %s '%s' contains an empty statement 
  EMPBLK {level="2"} // Module %s has an empty block 
  IGNSTR {level="2"} // Signal strength values are being ignored 
  LIBIMP {level="2"} // '%s' is supported only in library cells 
  NOSPEC {level="2"} // Specify block in module %s is ignored 
  INIMEM {level="2"} // Initialization of memory %s in module %s is ignored 
  NOGATE {level="2"} // Module %s contains unsupported gate type %s 
  NOSWTC {level="2"} // Module '%s' contains non-synthesizable switch type '%s' 
  NOWIRE {level="2"} // Module %s contains node %s of unsupported trireg type 
  FSETGV {level="2"} // Function '%s' in module '%s' assigns a value to global variable '%s' 
  FTNNAS {level="2"} // HDL statement after function assignment return statement in function '%s' in module '%s' 
  FUSEGV {level="2"} // Function '%s' in module '%s' uses global variable '%s' 
  TSETGV {level="2"} // Task '%s' in module '%s' assigns a value to global variable '%s' 
  TUSEGV {level="2"} // Task '%s' in module '%s' uses global variable '%s' 
  USEPAR {level="2"} // %s '%s' defined in %s '%s' is unused 
  USEENM {level="2"} // Enum variable '%s' defined in %s '%s' is unused 
  USEWIR {level="2"} // Wire '%s' defined in module '%s' is unused 
  USEREG {level="2"} // Local register variable '%s' defined in %s '%s' is unused 
  USETSK {level="2"} // %s '%s' defined in %s '%s' is unused 
  INTEGD {level="2"} // Delay expression is not an integer 
  CONSTD {level="2"} // Delay is not a constant expression 
  DLNBLK {level="2"} // Delay in non-blocking assignment; delay will be ignored 
  NULPRT {level="2"} // Module '%s' has null formal port(s) 
  UASWIR {level="2"} // Wire '%s' defined in %s '%s' is unassigned, but drives at least an object 
  UASREG {level="2"} // Local register variable '%s' is unassigned, but is read at least once in %s '%s' 
  URDWIR {level="2"} // Wire '%s' defined in %s '%s' does not drive any object, but is assigned at least once 
  URDREG {level="2"} // Local register variable '%s' is not read, but is assigned at least once in %s '%s' 
  URAWIR {level="2"} // Wire '%s' defined in %s '%s' is unused (neither read nor assigned) 
  URAREG {level="2"} // Local register variable '%s' defined in %s '%s' is unused (neither read nor assigned) 
  IMPNET {level="2"} // Net '%s' has an implicit declaration of type '%s' 
  IMPDTC {level="2"} // Expression '%s' implicitly converted to type 'unsigned' from type 'signed' 
  IMPTYP {level="2"} // Expression '%s' implicitly converted to type '%s' from type '%s' 
  IPUFSE {level="2"} // Expression '%s' implicitly converted to type 'signed' from type 'unsigned' 
  IPSFOU {level="2"} // Signal/Constant '%s' implicitly converted to type 'signed' from type 'unsigned' 
  CXZSIG {level="2"} // In module '%s', assignment statements corresponding to '%s' item has a non-constant driver 
  RDBFAS {level="2"} // Register '%s', assigned using blocking assignment, is being read before getting assigned 
  REVROP {level="2"} // Register '%s' is being read/assigned outside the process in which it was assigned using a blocking assignment 
  PRMNAM {level="2"} // Passing of parameters to instance '%s' of module '%s' should be done by name rather than by position 
  EXPIPC {level="2"} // Formal port '%s' of instance '%s' is connected to an expression 
  FORINT {level="2"} // Variable '%s' is not initialized before being incremented/decremented in the for loop 
  FINBLK {level="2"} // The final block of module '%s' does not contain any display statement 
  STRREL {level="2"} // String %s is used in the relational operation '%s' 
  PRMSZM {level="2"} // Parameter '%s' has a size mismatch between module instantiation and declaration 
  POIASG {level="2"} // The result of %s operation may lead to a potential overflow 
  FCWDEF {level="2"} // Redundant case expression -- full_case has a default case 
  SGNUSG {level="2"} // Negative value '%s' assigned to an unsigned variable '%s' 
  OVRDRT {level="2"} // The return statement will override the value assigned to the function name 
  CAFDEF {level="2"} // 'default' is not the last item of case statement 
  BITUNS {level="2"} // Not all bits of constant '%s' are explicitly specified 
  RDNTCX {level="3"} // Casex usage is redundant as none of the case item expression contains 'x', 'z', or '?' 
  RDNTCZ {level="3"} // Casez usage is redundant as none of the case item expression contains 'z' or '?' 
  NOINCD {level="3"} // Compiler directive `include should not be used 
  FNAVPC {level="1"} // Function %s 
  MLPSGS {level="2"} // Multiple %s signals used in flip-flop '%s' 
  RDOPND {level="3"} // Expression contains redundant %s 
  IOPNTA {level="2"} // Port '%s' should not be of mode inout 
  NSTIFD {level="2"} // The ifdef directive has exceeded three levels of nesting 
  SNOROP {level="2"} // Logical/Bitwise OR operator used in the sensitivity list 
  INDXOP {level="2"} // An operator is used in the index of the array '%s' 
  LMULOP {level="2"} // The result of the multiplication operation exceeds '%d' bits 
  NCASEX {level="3"} // 'casex' statement used in module '%s' 
  NFCASE {level="3"} // 'full_case' synthesis directive used in module '%s' 
  NOUNDF {level="3"} // Macro defined using `define statement is not undefined using `undef statement in module '%s' 
  NODEFD {level="3"} // Compiler directive `define should not be used 
  NETDCL {level="3"} // %s '%s' is not declared prior to non-declarative statement(s) or does not follow the recommended declaration sequence 
  BUSREV {level="3"} // Formal '%s[%d:%d]' port is connected in opposite order with the actual port(s) 
  INCLDR {level="4"} // Absolute or relative path specified with the `include compiler directive 
  PIMBIT {level="2"} // Primitive input port (port index : %d ) is connected to signal/expression with multiple bits. Reduction OR logic is being applied 
  IFMULT {level="2"} // Conditional expression '%s' completely overlaps one or more branches of the 'if-else' block 
  LOOPTM {level="2"} // Logic or Relational operation between a loop variable and a non-constant value is repeated more than %d times 
}

category RTL_CODINGSTYLE_VHDL "VHDL only coding style checks" default_on
{
  NOSHFT {level="1"} // Shift operator %s with signed shift count is not synthesizable 
  INTCON {level="1"} // VHDL signal '%s' of type integer is not constrained 
  NEGRNG {level="1"} // Index range of integer signal '%s' is '%d' 
  ENBFLK {level="1"} // Port '%s' should not be of mode buffer or linkage 
  SYNCSL {level="1"} // The sensitivity list of a sequential process does not contain an asynchronous reset 
  MLTCLK {level="1"} // The sequential process contains more than one clock signal 
  CLKEDG {level="1"} // Both edges of clock signal '%s' are used in a sequential process 
  GATCLK {level="1"} // Gated clock signal '%s' is not properly formed/used 
  BADCON {level="1"} // Bad VHDL construct '%s' is being used 
  FTNRET {level="1"} // Function '%s' declared in architecture '%s' does not return a value 
  INVBAS {level="1"} // Invalid base (%d) used in VHDL based literal 
  ENTDCL {level="2"} // A VHDL entity should only consist of generic and port interface lists 
  RTLINI {level="2"} // A variable/signal '%s' in an RTL description is initialized in its declaration 
  GENTYP {level="0"} // The generic '%s' is not of an authorized type 
  PRTTYP {level="2"} // Port '%s' is not of an authorized type (std_logic, std_logic_vector, signed, unsigned) 
  SEQVAS {level="2"} // VHDL variable '%s' is used to register data 
  UNITNM {level="2"} // VHDL design-unit name '%s' is missing on the end line 
  SUBPNM {level="2"} // VHDL %s name '%s' is missing on the end line 
  NOLABL {level="2"} // Process label '%s' is missing as a closing label 
  ALOWID {level="2"} // Signal/variable name '%s' does not follow the active-low naming convention 
  NOALIA {level="2"} // Aliases should not be used 
  SPSIGA {level="2"} // Subprogram assigns a value to signal '%s' 
  SUBTNM {level="2"} // Subtype name '%s' does not contain the type name '%s' 
  NRTLWT {level="2"} // Sensitivity lists should be used instead of wait statements 
  CECONC {level="2"} // Concatenation operation used in conditional expression 
  FENAME {level="2"} // Identifier '%s' updated on negative edge of clock should have '_f' as suffix 
  POIASG {level="2"} // The result of %s operation may lead to a potential overflow 
  GLBSIG {level="2"} // Global signal '%s' is being used in architecture '%s' 
  USRATW {level="2"} // User-defined attribute '%s' is being used in architecture '%s' 
  ONELIB {level="2"} // Single library declaration clause used to declare multiple library names 
  PROSIG {level="2"} // Signal '%s' defined in architecture '%s' is used inside only one process. Use variable instead 
  PRTMOD {level="2"} // Port mode mismatch in '%s' component declaration for port '%s'. Declaration is of mode %s, entity port declaration is of mode %s 
  PUSEGV {level="2"} // Procedure '%s' in design-unit '%s' uses global variable '%s' 
  WRKLIB {level="2"} // Library '%s' should not be referenced in the design 
  CALABL {level="2"} // Concurrent signal assignment used to express behavior requires a label 
  FTNPMC {level="2"} // Parameter '%s' of function '%s' has missing/incorrect mode and/or object class 
  PROPMC {level="2"} // Parameter '%s' of procedure '%s' has missing/incorrect mode and/or object class 
  ENTPMC {level="2"} // No mode specified for port '%s' in entity declaration 
  COMPMC {level="2"} // No mode specified for port '%s' in component declaration 
  LPEXIT {level="2"} // Loop contains an exit or next statement 
  RECTYP {level="2"} // Record type '%s' should not be used 
  USELIB {level="2"} // Library '%s' is declared, but no object is used from it 
  LINPRT {level="2"} // Port '%s' of mode linkage does not form part of the layout convention 
  GLBRES {level="2"} // Global signal '%s' is of resolved type 
  IDXMIS {level="2"} // Port '%s' has index bounds mismatch between component instantiation '%s' and entity declaration '%s' 
  UASVAR {level="2"} // Variable '%s' is unassigned, but is read at least once in %s '%s' 
  URAVAR {level="2"} // Variable '%s' defined in %s '%s' is unused (neither read nor assigned) 
  URDVAR {level="2"} // Variable '%s' is not read, but assigned at least once in %s '%s' 
  UASSIG {level="2"} // Signal '%s' is unassigned, but is read at least once in %s '%s' 
  URASIG {level="2"} // Signal '%s' defined in %s '%s' is unused (neither read nor assigned) 
  URDSIG {level="2"} // Signal '%s' is not read, but assigned at least once in %s '%s' 
  USCNST {level="2"} // Constant '%s' defined in %s is unused 
  FILTXT {level="2"} // File specified with file variable '%s' is not of type TEXT 
  ABSPAT {level="2"} // Absolute path specified for file variable '%s' 
  MAXPRT {level="3"} // Entity '%s' must not have more than %d ports 
  MLITNU {level="3"} // The enumeration type '%s' should not contain more than %d literals 
  STDPKG {level="3"} // The IEEE package '%s' should not be used 
  DESULN {level="3"} // The length of design-unit '%s' should not exceed %d lines 
  INSTLB {level="3"} // Component instance label '%s' exceeds %d characters 
  MISUSC {level="3"} // Library '%s' is used without a 'use' clause 
  PWTHWT {level="2"} // Process block with no sensitivity list is without a wait statement 
  CDNWOT {level="1"} // Case statement without 'when others' clause 
}

category RTL_CODINGSTYLE_MIXED "coding style checks for Verilog and VHDL" default_on
{
  TFARGT {level="1"} // %s/function call argument %d is of wrong type (%s vs. %s) 
  TFARGN {level="1"} // Task/function call has wrong number of arguments 
  UNCONN {level="1"} // %s port '%s' defined in design-unit '%s' is not connected in its instance '%s' 
  UNCONI {level="1"} // Input port '%s' of entity/module '%s' is being used inside architecture/module, but not connected (either partially or completely) in its instance '%s' 
  UNCONO {level="1"} // Port '%s' (which is being used as an output) of entity/module '%s' is being driven inside the design, but not connected (either partially or completely) in its instance '%s' 
  CONSTC {level="1"} // Constant conditional expression encountered 
  CNSTCN {level="1"} // Conditional expression is statically evaluated to %s 
  SHFTNC {level="1"} // Shift by non-constant 
  UELCIT {level="1"} // Unequal length in case item comparison (selector is %d bits, case tag expression is %d bits) 
  UELOPR {level="1"} // Unequal length operand in bit/arithmetic operator %s 
  INTTOB {level="1"} // Assigning a 0 or 1 (32 bits) to a single-bit variable 
  CNSTCI {level="1"} // Case item expression is not a constant 
  TRUNCC {level="1"} // Truncation of bits in a constant.  The most significant bits are lost 
  TRUNCZ {level="1"} // Truncation in constant conversion without a loss of bits 
  ULRELE {level="1"} // Unequal length operands in relational operator (padding produces incorrect result) -- LHS operand is %d bits, RHS operand is %d bits 
  ULCMPE {level="1"} // Unequal length operands in equality operator encountered (padding produces incorrect result). LHS operand is %d bits, RHS operand is %d bits 
  CEXPOR {level="1"} // Case item expression out of range 
  CIMULT {level="1"} // Case item expression covered more than once (covers same case item expression as in line %d) 
  DNGLEL {level="1"} // Ambiguous else statement in the nested if statement. It is recommended to enclose the inner if statement in a begin/end block 
  OOBIDX {level="1"} // %s '%s' (%s) is outside the defined range (%d to %d) 
  NULLRG {level="0"} // In design-unit/module %s, %s %s has null range defined 
  IDXRNG {level="1"} // Loop index is too small for the values it should take 
  CNREAL {level="1"} // Real variable %s is used in %s %s. Real variables are not synthesizable 
  CNINTB {level="1"} // Converting integer to a single-bit constant 
  INFLOP {level="1"} // %s %s possibly contains an infinite loop 
  MISSEL {level="1"} // Signal '%s' missing from sensitivity list of a sequential process/block 
  USESEL {level="1"} // Signal '%s' should not be used in the sensitivity list of a sequential process/block 
  NOTECH {level="1"} // Instance '%s' is instantiating a technology cell. Avoid using technology cells in the design 
  POOBID {level="1"} // Variable index/range selection of '%s' is potentially outside the defined range 
  IDXTSM {level="1"} // Variable index/range selection of '%s' is too small to access its defined range completely 
  NEQPRM {level="1"} // Size mismatch between formal %s parameters of function '%s' 
  ASNRST {level="1"} // %s '%s' has '%s' asynchronous set/reset '%s' as against the recommended '%s' style 
  SNCRST {level="1"} // %s '%s' has '%s' synchronous set/reset '%s' as against the recommended '%s' style 
  CBYNAM {level="1"} // Port connections for instance '%s' of %s '%s' should be made by name rather than by positional ordered list 
  SYNPRT {level="1"} // Output port '%s' is assigned asynchronously 
  CDEATF {level="1"} // Conditional expression always evaluates to %s 
  PBYNAM {level="2"} // Named association should be used in the parameter list for %s call '%s' 
  TIESUP {level="2"} // The output/inout '%s' is tied to supply0/supply1 
  TIELOG {level="2"} // The output/inout '%s' is assigned a constant logic value 
  TFWARG {level="2"} // Too few arguments passed to switch/gate 
  BOUINC {level="2"} // Lower bound of '%s' is not '%d' 
  INPASN {level="2"} // Assignment to a %s %s '%s' is not supported 
  DCLSCP {level="2"} // Variable '%s' defined in scope '%s' is also defined in parent scope '%s' 
  UNDRIV {level="2"} // Primary output/inout '%s'  is not driven in the %s '%s' 
  PUNDRV {level="2"} // Primary output/inout '%s'  is not fully driven in the %s '%s' 
  CNSTLT {level="2"} // Literal '%s' should be replaced with a constant 
  USEFTN {level="2"} // Function '%s' defined in %s '%s' is unused 
  USEPRT {level="2"} // The input/inout port '%s' defined in the %s '%s' is unused (neither read nor assigned) 
  UASPRT {level="2"} // The input/inout port '%s' defined in the %s '%s' is unassigned, but read 
  URDPRT {level="2"} // The input/inout port '%s' defined in the %s '%s' is unread, but assigned 
  SHFTOF {level="2"} // Shift overflow, some bits will be lost 
  REALCM {level="2"} // Real operand used in logical comparison 
  BSINTT {level="2"} // Bit/part select of integer or time variable '%s' encountered 
  EXTEND {level="2"} // Extension of '0' bits in a constant 
  PADMSB {level="2"} // Constant '%s' will be left-padded by %d '0' bits 
  NULCSE {level="2"} // Null statement should not be used in 'when others' clause in the case statement 
  REALCT {level="2"} // Real comparison in case expression 
  WIDSEL {level="2"} // Case statement with no default. Case is too wide to check if all cases are covered 
  NESTIF {level="2"} // Nested ifs. Consider using a %s statement instead 
  MEMSIZ {level="2"} // Memory declaration for '%s' defines a single-bit memory word. Check for error in register declaration 
  OUTINP {level="2"} // Primary output port %s of module %s may be driven outside the module 
  RDREAL {level="2"} // Real literal is rounded to the nearest integer 
  CNTIME {level="2"} // Time variable %s is used in %s %s. Time variables are not synthesizable 
  FTNEXT {level="2"} // Function '%s' must have only one return statement, which is the last statement in the function 
  UNRCHC {level="2"} // Code written after an unconditional return, break or continue statement is not reachable 
  FFASMX {level="2"} // In the specified always/process block, descriptions of flip-flops with and without asynchronous set/reset are mixed. Flip-flops without asynchronous set/reset are: %s 
  AVDREC {level="2"} // Function '%s' is called recursively in %s '%s' 
  LMTSTS {level="2"} // The number of states %d should be limited to %d 
  NUMSUF {level="2"} // Identifier '%s' has a numeric value suffix 
  STYVAL {level="3"} // Numeric value '%d' used for identifier '%s'. Use constants to avoid portability issues 
  SYNSCU {level="3"} // Embedded synthesis script used in the design 
  MPCMPE {level="3"} // Expression uses '%d' operands without parentheses, which exceeds the recommended limit of '%d' operands 
  LDFFPI {level="1"} // The logic depth between %s '%s' and %s '%s' is more than %s 
  DFLDER {level="0"} // Parameters specified are incorrect, check LDFFPI will be ignored 
  TRIWAR {level="2"} // Tristate logic inferred in %s block 
  TBNNAM {level="2"} // Testbench module/entity '%s' does not follow the recommended naming convention 
  TBNSTP {level="2"} // '$stop' used in testbench module/entity '%s' 
  IPRTEX {level="2"} // %s is used in a port expression 
  PRMEXP {level="2"} // %s '%s' used in a port expression 
  USEPKG {level="2"} // Package '%s' is declared but no object is used from it 
}

category RTL_CODINGSTYLE_ASSERTIONS "coding style checks for Assertions" default_off
{
  OOMRNM {level="4"} // Hierarchical reference '%s' passed as the DUT signal to %s '%s' 
  LABMIS {level="4"} // %s identifier '%s' not specified in the corresponding %s statement 
}

category RTL_SIMRACE_VERILOG "Verilog only simulation race condition checks" default_on
{
  RWRACE {level="0"} // A read/write race exists between '%s' and '%s' 
  WWRACE {level="0"} // '%s' is written in more than one process 
  TRRACE {level="0"} // A trigger-propagation race exists between '%s' and '%s' 
  NBCOMB {level="1"} // Non-blocking assignment encountered in a combinational block 
  BLKSQB {level="1"} // Blocking assignment encountered in a sequential block 
  BLNBLK {level="1"} // Signal '%s' is assigned via both blocking and non-blocking assignments 
}

category RTL_SIMSYNTH_VERILOG "Verilog only pre and post-synthesis simulation mismatch checks" default_on
{
  EVTRIG {level="0"} // Always block with no event trigger at the start of the block in module '%s' 
  LPVRMA {level="0"} // The loop variable '%s' is used in multiple always blocks 
  METAEQ {level="0"} // In module %s, %s comparison is treated as %s 
  METACX {level="1"} // In %s '%s', case/casez item expressions evaluating to 'x' are ignored 
  METACZ {level="1"} // In %s '%s', case item expressions evaluating to 'z' are ignored 
  CODNCR {level="2"} // Signal '%s' used in conditional expression has don't care value 
  EXLTRS {level="2"} // Expression used in the conditional logic of tristate buffer '%s' 
}

category RTL_SIMSYNTH_MIXED "Verilog/VHDL pre and post-synthesis simulation mismatch checks" default_on
{
  SYNTXZ {level="0"} // Synthesizing 'x'/'z' values in %s '%s' 
  INCSEL {level="0"} // '%s' missing from sensitivity list 
  METACO {level="0"} // In module %s, %s having 'x'/'z' statically evaluated to false 
  EXTENX {level="1"} // Extension of 'x' bits in a constant 
  EXTENZ {level="1"} // Extension of 'z' bits in a constant 
  SLVMOD {level="1"} // Identifier '%s' appearing in the sensitivity list is modified inside the block 
  SLRANG {level="1"} // Range '%s' used in the sensitivity list is not complete. This could lead to differences in simulation/synthesis 
  SLVUSE {level="1"} // Variable '%s' appearing in the sensitivity list is not used in the %s block 
  MXTSBC {level="1"} // Node '%s' has '%d' tri-state buffers connected, which exceeds the recommended limit of '%d' 
  TSBNTH {level="1"} // Logic driven by tri-state buffer '%s' is not in a separate module 
  XZDVAL {level="2"} // Delay value contains an x/z 
  IGNDLY {level="2"} // Lumped delay in %s '%s' is ignored 
  BITUSD {level="2"} // The bus variable '%s' appears in the sensitivity list, but all the bits are not used within the block 
  HASLEX {level="2"} // The design contains 'synthesis_off/synthesis_on' pragmas 
  MDLDCL {level="2"} // Signal '%s' is declared as '%s'. Use of '%s' can lead to simulation/synthesis mismatch 
  HASPGM {level="2"} // The design contains pragma directives 
  LEXPGM {level="2"} // File contains lexical pragmas, however it is not compiled with pragma/lexpragma command-line option 
  PRBULT {level="2"} // Pragma '%s' is being applied to function 
  FASNSR {level="1"} // In module/design-unit '%s', flip-flop has both asynchronous set and reset signals 
}

category RTL_SYNTH_VERILOG "Verilog only synthesizability checks" default_on synth_only
{
  EVTINV {level="0"} // The specified event expression cannot be synthesized 
  EVTDCL {level="0"} //  
  EVTCTL {level="0"} // Module %s contains non-synthesizable named event control %s 
  NOFREL {level="0"} // %s %s contains non-synthesizable force/release constructs 
  NOWAIT {level="0"} // %s %s contains non-synthesizable wait construct 
  NOFORE {level="0"} // Module '%s' contains non-synthesizable forever construct 
  NOFKJN {level="0"} // %s %s contains non-synthesizable fork-join constructs 
  NFOREV {level="0"} // Module %s contains unsupported forever construct 
  USGTSW {level="0"} // "%s" not supported 
  PTYPUS {level="0"} // In design-unit %s, ports of type "%s" are not supported 
  NONOWF {level="0"} // 'now' function in design-unit %s is not synthesizable 
  AMODNS {level="0"} // Aliased modules are not supported by default. Module %s has duplicate input/inout ports which has effect of aliasing (shorting) two nets 
  INIEVN {level="0"} // Module %s contains non-synthesizable initial block with event control 
  NODSBL {level="0"} // Module %s contains unsupported disable construct 
  NSLOOP {level="0"} // %s %s contains non-static loop 
  NOEVRP {level="0"} // Module '%s' contains non-synthesizable repeat event specification 
  NEVREP {level="0"} // %s %s contains non-synthesizable repeat event specification 
  DPRUSP {level="0"} // Module %s has non-synthesizable defparam statement 
  MULWIR {level="0"} // Module '%s' has wire '%s%s' multi-driven 
  MUDREG {level="0"} // In module '%s', register '%s' is driven in more than one block or process 
  PCAUSP {level="0"} // Module %s has non-synthesizable assign/deassign statements 
  OOMRUS {level="0"} // %s %s has unsynthesizable OOMRs (Out-Of-Module Reference) 
  INAEVT {level="0"} // Module '%s' contains an unsupported intra-assignment event specification 
  USINEV {level="0"} // %s %s contains unsupported intra-assignment event specification 
  INTEVN {level="0"} // Module %s contains unsupported inter-statement event specification 
  CLKMIX {level="0"} // Always block has both level and edge sensitive nodes in its sensitivity list 
  HDLBND {level="0"} // Module '%s' specified through the 'bind_top' option has constructs other than bind statements specified in it. Only bind statements present in this module will be recognized and all other constructs will be ignored by the tool 
  NOIVAL {level="0"} // The initial value is missing in the declaration of constant '%s' 
  UNSINI {level="0"} // Increment/Decrement operators in the port connection of an instance are not supported by the tool. Remodel the design without using these operators 
  VLPMWL {level="0"} // Value of loop variable '%s' modified within the loop 
  TCLKED {level="0"} // %s of signal '%s' used in task '%s' 
  CELVEC {level="1"} // No re-timing will be done for %s cell 
  INFREC {level="1"} // %s %s possibly contains unbounded subprogram recursions 
  LRGARR {level="1"} // The given assignment has a very large variably indexed node on the left hand side, processing the statement may be very time-consuming 
  NOASLD {level="1"} // In module %s, asynchronous load is not inferred for node %s%s 
  MULNBA {level="1"} // In module '%s', register '%s' has multiple non-blocking assignments%s 
  MULBAS {level="2"} // In module '%s', register '%s' has multiple blocking assignments%s 
  UCLPNS {level="1"} // In design-unit '%s', an unconditional loop statement is encountered 
  MULIFF {level="1"} // Always block has multiple event controls with associated 'iff' qualifiers 
  ASNIFF {level="1"} // Always block has an asynchronous control with associated 'iff' qualifier 
  NOCOMB {level="1"} // The node '%s' models a %s in an 'always_comb' block 
  NLATCH {level="1"} // The node '%s' models a %s in an 'always_latch' block 
  NOFLOP {level="1"} // The node '%s' models a %s in an 'always_ff' block 
  MTCOND {level="1"} // The specified case statement with a 'unique' keyword has more than one case item that matches the case expression 
  NTCOND {level="1"} // The specified case statement with a 'unique' or 'priority' keyword does not have any case item that matches the case expression 
  IGPRAG {level="1"} // The tool does not support unique/priority constructs in edge sensitive sequential blocks. This construct will be ignored by the tool 
  NOLOCL {level="2"} // In %s %s, local nodes of task/function %s are initialized 
  INIUSP {level="2"} // %s %s has an initial block or a variable declaration assignment, which is ignored by synthesis tools 
  FINUSP {level="2"} // Module '%s' has a final block, which is ignored by synthesis tools 
  IGNIFF {level="2"} // The 'iff' qualifier, associated with the event expression with no edge specification, is ignored 
  FFLRFR {level="1"} // Flip-flop '%s' has reset/set and logic section in the same '%s' loop 
  FFALWR {level="1"} // The 'if' statement specifying an asynchronous %s '%s' is not the first statement of the always block 
  FFRSTV {level="1"} // The %s signal '%s' is inferred as a vector 
}

category RTL_SYNTH_VHDL "VHDL only synthesizability checks" default_on synth_only
{
  GENTYP {level="0"} // The generic '%s' is not of an authorized type 
  SHRVNS {level="0"} // Shared variables are not synthesizable 
  SHFTOP {level="0"} // In design-unit %s, non-synthesizable shift operation %s is encountered 
  GRDASN {level="0"} // In design-unit %s, non-synthesizable guarded assignments are encountered 
  WAITML {level="0"} // In design-unit %s, multiple edges are specified after wait-until statement 
  SLDIRW {level="0"} // Inconsistent direction in slice discrete range 
  NOEXPN {level="0"} // Exponentiation operator is not synthesizable 
  EXPCHR {level="1"} // Expecting character strings for encoding of user-defined enumeration types in VHDL 
  STDMBC {level="1"} // Call to STD_MATCH will result in boolean-value comparison 
  RECATT {level="1"} // Invalid use of attributes. Incorrect modeling style used 
  NONGEN {level="2"} // No default value specified for generic %s in design-unit %s 
  TOPGEN {level="2"} // Top-level design-unit '%s' has generic '%s' without a default value 
}

category RTL_SYNTH_MIXED "Verilog and VHDL  synthesizability checks" default_on synth_only
{
  RECFLE {level="0"} // No combinational circuit or sequential element could be recognized for %s.%s%s. The sensitivity list will be used as the trigger 
  AMSDES {level="0"} // Analog constructs detected in design %s 
  ARCONV {level="0"} // Array size/shape mismatch in explicit type conversion 
  NULLRG {level="0"} // In design-unit/module %s, %s %s has null range defined 
  NLCRNG {level="0"} // Range evaluates to a null range 
  LPNTEX {level="0"} // The loop range of the specified "for" loop is a null range 
  NSLOOP {level="0"} // %s %s contains non-static loop 
  VARRNG {level="0"} // Left and right bounds must be constant valued expressions 
  IMPFSM {level="0"} // %s %s contains implicit finite-state machine 
  SENCMW {level="0"} // Sensitivity list incomplete for node %s%s in %s. Missing signal(s): %s 
  OUTRNG {level="0"} // Bit/part select %s is outside the defined range %s 
  AWNDEL {level="0"} // %s block with no event trigger at the start in %s %s 
  CLKASY {level="0"} // For node %s in design-unit/module %s, clock signal %s is used in asynchronous control 
  CLKATR {level="0"} // For node %s in design-unit %s, non-synthesizable use of attribute event on %s 
  CLKBED {level="0"} // In module/design-unit %s, clock signal %s, for node %s, is driving data on both edges. Wrong polarity specified 
  CLKEXP {level="0"} // In module/design-unit '%s', for flip-flop '%s', clock is an expression 
  CLKMUL {level="0"} // In module %s, node %s has multiple clocks specified 
  CLKNED {level="0"} // In module/design-unit %s, clock signal %s for node %s does not drive any data. Wrong polarity specified 
  CLKOUT {level="0"} // In module/design-unit '%s', for flip-flop '%s', clock signal '%s' is used as the output 
  CLKSRD {level="0"} // In module/design-unit '%s', clock signal '%s', for flip-flop '%s', is used as %s 
  OPRUSP {level="0"} // Module %s has unsynthesizable '%s' operation 
  RSTEXP {level="0"} // In module/design-unit '%s', for flip-flop '%s', reset is an expression 
  OUTORG {level="0"} // Range constraint violation in design-unit %s 
  PRTNLL {level="0"} // A port of this instance is considered as undriven due to the presence of unsupported construct(s) 
  DRPBLK {level="0"} // The %s is being ignored due to the presence of unsupported construct(s) 
  SFNUNS {level="0"} // System function calls are not synthesizable 
  LOCOFA {level="0"} // Loop condition is false 
  XINASN {level="0"} // In module/design-unit '%s', asynchronous set/reset signals of the flip-flop has value x 
  LATBAS {level="0"} // In module/design-unit %s, latch is assigned by blocking assignments 
  MISNOD {level="0"} // '.*' could not infer any implicit port connection corresponding to port %s. This port will be left unconnected. 
  TXTPNS {level="0"} // In design-unit %s, unsupported procedure call %s from text packages encountered 
  UNSCON {level="0"} // Unsupported declaration/construct, will be ignored: %s 
  USATYP {level="0"} // In design-unit %s, objects of unsupported access type are encountered 
  INTTAG {level="0"} // In module %s, integer tags have been re-sized. This can cause a simulation mismatch 
  NOACCD {level="0"} // In design-unit %s, unsupported access type declaration encountered 
  NOALLD {level="0"} // In design-unit %s, unsupported allocator/deallocate is encountered 
  NOASST {level="0"} // In design-unit %s, unsupported assertion statement is encountered 
  PHYSNS {level="0"} // Literal physical data in design-unit %s is not supported 
  NOCASS {level="0"} // In design-unit %s, unsupported concurrent assertion statement is encountered 
  USFTYP {level="0"} // In design-unit %s, objects of unsupported file type are encountered 
  NODSCN {level="0"} // Disconnect specification in design unit %s not supported 
  USUPTE {level="0"} // Unsupported Table Entry 
  FILENS {level="0"} // File type declarations are not synthesizable and will be ignored 
  FILEOP {level="0"} // In design-unit %s, file operation %s is not synthesizable 
  BOXERR {level="0"} // Module/Design-unit %s is being blackboxed with option %s and simultaneously being glassboxed with the -GB_LIST option 
  TBBERR {level="0"} // Specified top %s is not available in the design hierarchy because instance %s of module %s is blackboxed under option %s 
  TBXERR {level="0"} // Specified top %s is also blackboxed under option %s; therefore this tool is unable to process the specified sub-design 
  IFINST {level="0"} // SystemVerilog Interface instance '%s' is connected to instance '%s' defined as a user-defined top 
  IGNINS {level="0"} // The instance '%s' in module/DU '%s' has been dropped because of errors on the formal ports of the module it is instantiating 
  INVCOE {level="0"} // Expression with invalid concatenation repeat count is being ignored 
  INVGEN {level="0"} // The specified generic/parameter does not have a valid value 
  MNTPMX {level="0"} // The (minimum, typical, maximum) delay expression is ignored, because delays are not considered during functional verification 
  LANERR {level="0"} // Design has wrong language construct for %s package 
  LRGMOD {level="0"} // The total size of the module %s is greater than that can be processed by the tool 
  NCMNOA {level="0"} // Actual argument of type attribute to nc_mirror is not supported. The nc_mirror procedure will be ignored 
  NCMNOD {level="0"} // The %s %s you have passed to nc_mirror call does not exist. The nc_mirror procedure will be ignored 
  NCMOMR {level="0"} // OOMR is not supported for destination in nc_mirror. The procedure will be ignored 
  NCMSLC {level="0"} // Indexed/Slice expressions are not supported as destination or source in nc_mirror 
  NULSLC {level="0"} // Null slice range of slice expression encountered 
  SLDIRE {level="0"} // Inconsistent direction in slice discrete range 
  STMISM {level="0"} // There is a mismatch between the size of connecting variable and the instaniated module port. The instance with the implicit port connection will be ignored. Use explicit named or positional connection syntax 
  UNSPTP {level="0"} // Top-level module/entity has ports of unsupported types 
  UNSYNT {level="0"} // The statement has an unsynthesizable expression and will be ignored by the tool. Modify the design for proper functioning of the tool 
  LHSCON {level="0"} // A constant expression has been encountered on the left hand side of an assignment. The instances of this module will be ignored 
  USTYPE {level="0"} // In design-unit %s, "%s" type is not supported 
  ARSHMM {level="1"} // Array size/shape mismatch 
  COMBLP {level="1"} // In %s %s, combinational loop detected for node %s 
  PACSIG {level="1"} // In design-unit %s, read/write operation is performed on signal "%s" which is declared in package "%s" 
  FNORET {level="1"} // Function has no return value and function return type is unconstrained 
  WNORET {level="1"} // Function has no return value 
  ASNCLD {level="1"} // In module %s, asynchronous load is inferred for node %s%s. A synchronous reset may also be generated, if there is an error in the polarity of the reset signal 
  CELLOP {level="1"} // Cell %s may have combinational loops. Node %s is one of the nodes contributing to this potential loop 
  CLKINP {level="1"} // In %s '%s', clock signal '%s' for flip-flop '%s' is not an input 
  CLKLST {level="1"} // For node %s in design-unit/module %s, assignment under the clock single-edge condition expression must be the last assignment at this level and there must not be any assignment when this condition is false after this assignment 
  CLKMBT {level="1"} // In %s '%s', multi-bits '%s' used as clock for flip-flop '%s' 
  CLKMED {level="1"} // Node %s in design-unit/module %s, is being driven at %s 
  RSTINP {level="1"} // In %s '%s', reset signal '%s', for flip-flop '%s', is not an input 
  BLKBOX {level="1"} // %s %s automatically blackboxed 
  RLRINT {level="1"} // Real literal is rounded to the nearest integer 
  IGNENC {level="1"} // Enum encoding of the enum type is being ignored 
  EMTFNC {level="2"} // Function definition has an empty body 
  PGMENB {level="2"} // Statements from lines %d to %d, in the source file "%s", are under "verification_on/off" pragma. These statements will be processed 
  PGMIGR {level="2"} // Statements from lines %d to %d, in the source file "%s", are under "synthesis_off/on" pragma. The semantics of the design may differ from simulation semantics 
  PGMTSO {level="2"} // Basetype/subtype of "%s" has declaration under "synthesis_off/on" pragma 
  PGMUSO {level="2"} // "%s" has declaration under "synthesis_off/on" pragma 
  SKPSUP {level="2"} // Assignment to a supply0/supply1 net %s in %s %s is ignored 
  EMPBLK {level="2"} // Module %s has an empty block 
  RSTOUT {level="2"} // In module/design-unit %s, for flip-flop %s, reset signal %s is used as the output 
  EMPMOD {level="2"} // Module/Design-unit '%s' is empty 
  IGNATP {level="2"} // Ignoring attribute parameter on attribute %s 
  EXPBBX {level="3"} // Design contains explicitly blackboxed design units 
  EXPGBX {level="3"} // Design contains explicitly glassboxed design units 
  AUTOBX {level="3"} // Design contains automatically blackboxed design units/memories 
}

category FSM "Verilog and VHDL, FSM coding style checks" default_on synth_only
{
  FSMIDN {level="0"} // In module/design-unit '%s', FSM for state register '%s' has been recognized 
  TERMST {level="0"} // In module/design-unit '%s', FSM for state register '%s' has terminal states %s 
  UNRCHS {level="0"} // In module/design-unit '%s', FSM for state register '%s' has unreachable states %s 
  BADFSM {level="1"} // In module/design-unit '%s', FSM for state register '%s' does not adhere to modeling style guidelines 
  PTRMST {level="1"} // In module/design-unit '%s', FSM for state register '%s' has potentially terminal states %s 
  PUNRCS {level="1"} // In module/design-unit '%s', FSM for state register '%s' has potentially unreachable states %s 
  VARTAG {level="1"} // The specified FSM contains a variable case expression in the combinatorial logic 
  VARTRN {level="1"} // The specified FSM contains state transitions expressed as assignments of variables to the state register 
  EXTSEQ {level="1"} // Extraneous logic is present in the sequential portion of the FSM 
  PRMFSM {level="1"} // Parameter is not used to encode state of the FSM 
  EXTFSM {level="2"} // Extraneous logic present in module/design-unit '%s' that encodes an FSM%s 
  TRNMBT {level="2"} // For the specified state '%s', the state value changes by more than one bits on transition to state(s): %s 
}

category DFT "Verilog and VHDL DFT checks" default_on synth_only
{
  CMBPAU {level="0"} // Combinational path detected through '%s' in module/design-unit '%s' 
  ASNCFL {level="0"} // Asynchronous feedback loop detected through set/reset of flip-flop(s) and '%s' in module/design-unit '%s' 
  MULMCK {level="1"} // Multiple master clocks found. Clock '%s' for flip-flop '%s' is derived from master input '%s' while the previously detected clocks were derived from '%s' for flip-flop '%s' 
  FFCKNP {level="0"} // Flip-flop '%s' has clock '%s' which is not derived from master input 
  GTDCLK {level="0"} // Clock gating detected for clock '%s' of flip-flop '%s' 
  FFWASR {level="0"} // Flip-flop '%s' does not have any %s %s 
  FFWNSR {level="0"} // Flip-flop '%s' does not have any set or reset 
  FFASRT {level="0"} // Flip-flop '%s' has %s %s %s 
  ACNCPI {level="0"} // Asynchronous %s '%s' of latch/flip-flop '%s' is not controllable from primary inputs 
  LENCPI {level="0"} // Enable of latch '%s' is not controllable from primary inputs 
  CLKINF {level="0"} // Clock '%s' has associated DFT violations. It was inferred as clock because it drives the %s pin of %s '%s' 
  CLKDAT {level="0"} // Clock signal '%s' drives the data pin of flip-flop '%s' 
  CLKLDT {level="0"} // Clock signal '%s' drives the data pin of latch '%s' 
  CDFDAT {level="0"} // Clock signal '%s' drives the data pin and clock pin %s of flip-flop '%s' 
  CDLDAT {level="0"} // Clock signal '%s' drives the data pin and clock pin %s of latch '%s' 
  CAAFSR {level="0"} // Clock signal '%s' drives a set or reset pin of flip-flop '%s' 
  CACSRF {level="0"} // Clock signal '%s' drives set/reset and clock pin %s of flip-flop '%s' 
  CACSRL {level="0"} // Clock signal '%s' drives set/reset and clock pin %s of latch '%s' 
  CAALSR {level="0"} // Clock signal '%s' drives a set or reset pin of latch '%s' 
  RSTDAT {level="0"} // Reset signal '%s' drives the data pin of %s '%s' 
  LATINF {level="0"} // Process/always block models a latch, or signal '%s' is not assigned a value in all branches 
  LCNSTD {level="0"} // Inferred latch '%s' has constant data 
  FFCSTD {level="1"} // Inferred flip-flop '%s' has a constant data input 
  MRSTDT {level="1"} // Mix of synchronous and asynchronous set/reset found. Synchronous set/reset detected in '%s' and asynchronous set/reset detected in '%s' 
  TPOUNR {level="1"} // Output '%s' of top-level module is not a register 
  NEFLOP {level="1"} // Flip-flop '%s' is triggered at the negative edge of clock '%s' 
  SLNOTP {level="1"} // Enable pin '%s' of the tristate buffer (driving inout pin '%s') is not directly controllable by primary input(s) 
  JKFFDT {level="2"} // Flip-flop '%s' models a JK flip-flop 
  LATRAN {level="2"} // Latch '%s' is %s enable while its driving flip-flop '%s' is also sensitive at %s edge of the clock 
  TCDFDT {level="0"} // In test mode, clock signal '%s' drives the data pin and clock pin %s of flip-flop '%s' 
  TCDLDT {level="0"} // In test mode, clock signal '%s' drives the data pin and clock pin %s of latch '%s' 
  TCKDAT {level="0"} // In test mode, clock signal '%s' drives the data pin of flip-flop '%s' 
  TCKLDT {level="0"} // In test mode, clock signal '%s' drives the data pin of latch '%s' 
  TMSCFF {level="0"} // Test mode signal '%s' is directly connected to %s '%s' of %s '%s' 
  ASRTSC {level="0"} // In test mode, asynchronous set/reset%s of flip-flop/latch '%s' is not controllable during scan capture 
  ASRTCL {level="0"} // In test mode, asynchronous set/reset%s of flip-flop/latch '%s' is active during scan shift 
  ASRTCK {level="0"} // Test clock '%s' drives asynchronous set/reset%s of flip-flop/latch '%s' 
  SEICLK {level="0"} // Clock '%s', not bypassed in scan shift mode, is connected to clock pin of following flip-flop(s) 
  SCICLK {level="0"} // Clock '%s', not bypassed in scan capture mode, is connected to clock pin of following flip-flop(s) 
  SMTCLK {level="0"} // Clock '%s', driven by %d test clock(s) in scan mode, is connected to clock pin of following flip-flop(s) 
  TXCNOP {level="0"} // Output '%s' of tie-x cell '%s' is connected to '%s' during scan mode 
  MEMNOP {level="0"} // Output '%s' of memory cell '%s' is connected to '%s' during scan mode 
  OUTMNR {level="0"} // Output '%s', of memory cell '%s', is not registered 
  INPMNR {level="0"} // Input '%s', of memory cell '%s', is not registered 
  MCKNDB {level="0"} // Write clock '%s' of memory cell '%s' is not disabled during test mode 
  WENNDB {level="0"} // Write enable '%s' of memory cell '%s' is not disabled during test mode 
  TENNOD {level="0"} // In test mode, tristate buffer '%s' does not drive 'Z' during scan shift operation 
  TENNOC {level="0"} // In test mode, enable of tristate buffer '%s' is not controllable during scan shift operation 
  RSTEDG {level="0"} // In test mode, signal '%s' is acting as active high set/reset as well as active low set/reset 
  NOTCLK {level="0"} // The following flip-flops, in clock domain '%s', are not controlled by any test clock 
  MULTCK {level="0"} // In test mode, test domain '%s' drives multiple clock domains 
  LTCHNT {level="1"} // Latch '%s' is not transparent in test mode 
  NOTSCN {level="0"} // Flip-flop '%s' is not scannable 
}

category STRUCTURAL "Verilog/VHDL structural checks" default_on synth_only
{
  LFLTSE {level="0"} // Latch '%s' is feeding latch '%s' having same enable%s 
  LFFTNE {level="0"} // Latch '%s' is feeding flip-flop '%s' which is triggered at the negative edge of latch enable%s 
  MLTDRV {level="0"} // Signal/register '%s' has multiple drivers 
  SUTHRU {level="0"} // Possible shoot-through due to this assignment 
  GLTASR {level="0"} // Combinatorial logic present in the path of asynchronous %s '%s' may lead to a glitch. One such affected flip-flop is '%s' 
  FDTHRU {level="1"} // Feedthrough detected from input '%s' to output '%s' 
  DFDRVS {level="1"} // Drivers of sub-parts of vector '%s' are not of same type 
  INFNOT {level="1"} // Ignoring %s '%s' with no fanout to module/design-unit outputs or child instances 
  CBPAHI {level="2"} // Combinatorial path crossing multiple units drives '%s' 
  DALIAS {level="2"} // Aliased constructs found. %s '%s' and '%s' have same drivers 
  NUMDFF {level="2"} // Number of single-bit D flip-flops present in the hierarchy is %s 
  PRTDUP {level="2"} // There are ports with the same name '%s' in module '%s' 
  ATLGLC {level="1"} // Glue logic inferred in top-level module/design-unit '%s' 
  EDGMIX {level="1"} // Both edges of clock signal '%s' used in %s 
  SYNASN {level="2"} // The module/design-unit '%s' contains synchronous as well as asynchronous logic 
  MCKDMN {level="2"} // In instance '%s', clocks belong to different clock domains 
  CLKGNP {level="2"} // The clock generation logic is placed in module/design-unit '%s', which also contains extraneous logic 
  CLKGNH {level="2"} // The clock generation logic for clock '%s' is not at the same or a higher hierarchical level as the module/design-unit to which the clock applies 
}

category CLOCKDOMAIN "Verilog/VHDL clock domain checks" default_on synth_only
{
  CLKDMN {level="0"} // Signal from clock domain '%s' is crossing into domain of clock '%s' at flip-flop '%s' without proper synchronization 
  INSYNC {level="1"} // %s based synchronizer detected at '%s' synchronizing from clock domain '%s' to clock domain '%s' 
  NSYLAT {level="1"} // Some instances of latch '%s' are not used as synchronizer 
}

category SCANCHAIN "Verilog/VHDL Netlist level scan chain checks" default_on
{
  PCNOTC {level="0"} // Partial scan chain (with formal '%s') in instance '%s', is not part of any of the complete scan chains of its parent scope 
  SLENEX {level="0"} // Scan chain (from '%s' to '%s') length is '%d' which exceeds the limit '%d' 
  SCNLEN {level="2"} // Scan chain (from '%s' to '%s') has length '%d' 
  WRSCNL {level="0"} // 'scanlengthlimit' is incorrectly specified in local.def file, taking its default value 
  DSCNCK {level="0"} // A part of scan chain starting from port '%s' is found to have clock '%s' in instance '%s', which is different from scan clock '%s' 
  DSCNEN {level="0"} // A part of scan chain starting from port '%s' is found to have scan enable '%s' in instance '%s', which is different from scan enable '%s' 
  NONSCN {level="0"} // All the instances of module/design-unit '%s' are not scannable 
}

category PD_NONSYNTH "Category of all the checks which are a cause of non-synthesizability of DU on Palladium, hence redirection to NC-Sim (simulator)" default_off synth_only
{
  ARSHMM {level="1"} // Array size/shape mismatch 
  AORAGG  // Array of record aggregates are not currently supported for arrays of unconstrained types. Remodel the design 
  AORCON  // Array of record created using concatenation of arrays of records is not supported. Remodel the design 
  DOMRNS  // Disable OOMR not supported 
  EMTFNC {level="2"} // Function definition has an empty body 
  GRDASN {level="0"} // In design-unit %s, non-synthesizable guarded assignments are encountered 
  NONOWF {level="0"} // 'now' function in design-unit %s is not synthesizable 
  MOMRNS  // OOMR assignment to an element of a multi-dimensional array or a verilog memory is not supported. Remodel your design 
  MUSOMR  // Memory has unsupported OOMR assignments in the design 
  NOPATT  // Pre-defined attribute %s in design-unit %s is not synthesizable 
  NULSTR  // Null strings are not supported 
  RNGEXP  // Type range has unsupported expressions. Only static constant expressions are allowed in the range 
  SFNUNE  // System function calls are not supported 
  SOMRNE  // OOMR subprogram (function/task) call is not supported 
  UNCMDL  // Unbound components exist with same name %s and different number of ports/port size 
  UNKGEN  // Design-unit/Module %s has Generic/Parameter of unsupported type 
  UXUASR  // Use of 'X' in assertions is not supported 
  UZUASR  // Use of 'Z' in assertions is not supported in scenarios other than bus-float checks 
  WAVFRM  // Multiple waveform elements are not supported. Existing in %s %s, node %s 
  INFLOP {level="1"} // %s %s possibly contains an infinite loop 
  INFREC {level="1"} // %s %s possibly contains unbounded subprogram recursions 
  NLCRNG {level="0"} // Range evaluates to a null range 
  RECATT {level="1"} // Invalid use of attributes. Incorrect modeling style used 
  UNOMSU  // OOMR on function/task %s using nodes outside the subprogram scope is not supported 
  VARRNG {level="0"} // Left and right bounds must be constant valued expressions 
  IMPFSM {level="0"} // %s %s contains implicit finite-state machine 
  CELLOP {level="1"} // Cell %s may have combinational loops. Node %s is one of the nodes contributing to this potential loop 
  AMODNS {level="0"} // Aliased modules are not supported by default. Module %s has duplicate input/inout ports which has effect of aliasing (shorting) two nets 
  CNREAL {level="1"} // Real variable %s is used in %s %s. Real variables are not synthesizable 
  INIEVN {level="0"} // Module %s contains non-synthesizable initial block with event control 
  TFWARG {level="2"} // Too few arguments passed to switch/gate 
  CLKATR {level="0"} // For node %s in design-unit %s, non-synthesizable use of attribute event on %s 
  CLKLST {level="1"} // For node %s in design-unit/module %s, assignment under the clock single-edge condition expression must be the last assignment at this level and there must not be any assignment when this condition is false after this assignment 
  CLKMED {level="1"} // Node %s in design-unit/module %s, is being driven at %s 
  ARCONV {level="0"} // Array size/shape mismatch in explicit type conversion 
  NSLOOP {level="0"} // %s %s contains non-static loop 
  EVTCTL {level="0"} // Module %s contains non-synthesizable named event control %s 
  USINEV {level="0"} // %s %s contains unsupported intra-assignment event specification 
  NEVREP {level="0"} // %s %s contains non-synthesizable repeat event specification 
  NFOREV {level="0"} // Module %s contains unsupported forever construct 
  NODSBL {level="0"} // Module %s contains unsupported disable construct 
  NOWAIT {level="0"} // %s %s contains non-synthesizable wait construct 
  UNDSBL  // Module %s contains unsupported style of disable construct 
  USGTSW {level="0"} // "%s" not supported 
  USSTRG  // Nodes of composite data types, having std_ulogic type or types derived from std_ulogic in array ranges is currently not supported 
  NULRGE  // Node of null range is encountered 
  NOGATE {level="2"} // Module %s contains unsupported gate type %s 
  UUSTYP  // In design-unit %s, use of "%s" type is not synthesizable 
  NBFUNC {level="2"} // Non-blocking assignment encountered in function '%s' 
  SYSVNC  // SystemVerilog construct: '%s' is unsupported by HDL-ICE, the RTL compiler of Palladium and the corresponding module would be redirected to NC-Sim 
}

category HDLICE_NOSUPP "Category of all the checks which are unsupported by HDL-ICE hence lead to redirection to SA Bin" default_off synth_only
{
  MUDREG {level="0"} // In module '%s', register '%s' is driven in more than one block or process 
  MULWIR {level="0"} // Module '%s' has wire '%s%s' multi-driven 
  HISTUS  // The System task/function '%s' is not supported by HDL-ICE, the RTL compiler of Palladium 
  SPDCLK  // Module 'SPDclkgen2' should be directed to SA 
  HIINIT  // The initial blocks are not supported by HDL-ICE, the RTL compiler of Palladium 
  NOFREL {level="0"} // %s %s contains non-synthesizable force/release constructs 
  UNDASS  // Deassign statements are not supported by HDL-ICE, the RTL compiler of Palladium 
  SYSVAP  // SystemVerilog construct: '%s' is not supported by HDL-ICE, the RTL compiler of Palladium 
  NOFKJN {level="0"} // %s %s contains non-synthesizable fork-join constructs 
}

category PALLADIUM "Category of all the checks to qualify design to run on Palladium" default_off synth_only
{
  MEMHIR  // A hierarchical reference to the design memory '%s' found in the testbench 
  OOMRDT  // OOMR '%s' from synthesizable module '%s' to non-synthesizable module '%s' found 
  OOMRTD  // OOMR '%s' from non-synthesizable module '%s' to synthesizable module '%s' found 
  NOSPEC {level="2"} // Specify block in module %s is ignored 
  TIMCHK  // Timing checks done in the testbench on the design input/output '%s' 
  DLYWIR  // Delayed net '%s' which is connected to input port '%s' is being driven through timing check '%s' 
  UNSSTR  // Unsupported %s strength '%s' passed between testbench and design '%s' through input/inout port '%s' 
  TRISTR  // For an interface net, all tristate drivers must have both 'strong' values 
  INTCLK  // An internal clock '%s' is detected in the design 
  CKFREQ  // The testbench generated a clock '%s' with Time Period '%d.%02d' '%s' 
  TBZCON  // Net '%s', driven by the output interface net '%s' of the design, is tested for 'Z' 
  TBXZDV  // The input/inout port '%s' of the design '%s' is driven by 'X' or 'Z' %s '%s' 
  TBZOMR  // The signal '%s' of design '%s' is driven by 'X' or 'Z' through out of module reference from the testbench 
  BADKWD  // Usage of the keyword "QTSACELL" in the module/DU name is incorrect 
  CNREAL {level="1"} // Real variable %s is used in %s %s. Real variables are not synthesizable 
  MEMLOP  // Memory '%s' is read or written within a loop in the design 
  SHFLAR  // The shift register has large shift_by operator '%s' in the design 
  HISTIG  // A System Task/Function '%s' in module '%s' will be ignored by HDL-ICE, the RTL compiler of Palladium 
  NSDTOP  // The DUV top '%s' is non-synthesizable 
  NSSCDT  // The SystemC DUV top '%s' is non-synthesizable 
  SYNTNC  // While doing partitioning for Co-simulation flow, the synthesizable %s '%s' is directed to NC-Sim because its hierarchical path has behavioral source 
  ICEVHD  // Module '%s' is directed to HDL-ICE despite the presence of constructs which are unsupported by HDL-ICE, because its hierarchical path contains VHDL entity 
  VLOGSA  // Module '%s' is directed to sa bin because a module below its hierarchy was redirected to sa bin 
  SAFORC  // %s '%s' cannot be forced to SA bin because it is in VHDL hierarchy 
  HDLFRC  // Module '%s' cannot be forced to HDL-ICE because a module under its hierarchy was directed to sa bin 
  SPDVHD  // Module 'SPDclkgen2' is found beneath VHDL. Redirected to HDL-ICE 
  NODLPD  // Interface signal '%s' between NC and Palladium has no driver or load in the palladium emulator 
  NNSNMD  // Non-synthesizable module/DU '%s' encountered in DUV 
  FCDTOP  // The synthesizable module/DU top '%s' is forced to NC-Sim (simulator) bin 
  FRCDUV  // The synthesizable %s '%s' under DUV top is forced to NC-Sim (simulator) bin 
  PGMIGR {level="2"} // Statements from lines %d to %d, in the source file "%s", are under "synthesis_off/on" pragma. The semantics of the design may differ from simulation semantics 
  PGMTSO {level="2"} // Basetype/subtype of "%s" has declaration under "synthesis_off/on" pragma 
  PGMUSO {level="2"} // "%s" has declaration under "synthesis_off/on" pragma 
  CONSTD {level="2"} // Delay is not a constant expression 
  DLNBLK {level="2"} // Delay in non-blocking assignment; delay will be ignored 
  IGNDLY {level="2"} // Lumped delay in %s '%s' is ignored 
  SYNTXZ {level="0"} // Synthesizing 'x'/'z' values in %s '%s' 
  XZDVAL {level="2"} // Delay value contains an x/z 
  METACX {level="1"} // In %s '%s', case/casez item expressions evaluating to 'x' are ignored 
  METACZ {level="1"} // In %s '%s', case item expressions evaluating to 'z' are ignored 
  METACO {level="0"} // In module %s, %s having 'x'/'z' statically evaluated to false 
  CASEZX {level="1"} // Case item expression contains 'x' for a casez statement (useful only in casex statements) 
  V2CONF  // Configuration file '%s' found for module '%s' is not supported by HDL-ICE, the RTL compiler of Palladium 
  VHDOMR  // The OOMR '%s' pass through VHDL instance '%s' 
  TESDLY  // %s '%s' contains delay statement in initial block. '%s' might be a part of testbench 
  DIFBIN  // The file '%s' comprises of modules/DUs/UDPs which are partitioned in different bins 
  MISTOP  // Instance top not specified on the command-line for performing Acceleration Policy checks 
  NOEXMT  // %s '%s' specified in the input file '%s' does not exist 
  NONBIN  // %s '%s' specified in the input file '%s' is directed to a non-existing  bin '%s' 
  MISFLD  // The '%s' field is missing for the %s '%s' in the input file '%s' 
  EXTCHR  // Extra characters found for %s '%s' at the end of the line in input file '%s' 
  VHDLSA  // The VHDL design-unit '%s' has been forced to Palladium simulation acceleration compiler (sa) in input file '%s' 
  MULENT  // Multiple entries for redirection are found for %s '%s' in the input file '%s' 
  MULOPT  // The option %s has been specified multiple times on the command line. Only the first %d specification(s) will be considered 
  MUINSD  // There are multiple instances of the same module/DU '%s' being used as the design top 
  SHRVNS {level="0"} // Shared variables are not synthesizable 
  SHVUNS  // In design-unit %s, use of shared variables is not synthesizable 
  PD_NONSYNTH   // Category of all the checks which are a cause of non-synthesizability of DU on Palladium, hence redirection to NC-Sim (simulator)
  HDLICE_NOSUPP         // Category of all the checks which are unsupported by HDL-ICE hence lead to redirection to SA Bin
  RTL_SIMRACE_VERILOG   // Verilog only simulation race condition checks
}

category ALL_TOOL "HAL usage errors" default_on
{
  SYSTMC  // Design contains SystemC(r) objects. HAL performs only linting checks on SystemC(r) objects 
  CMDNIM  // %s is not yet implemented 
  BADDEF  // Error reading message definitions file: %s 
  BADINF  // %s 
  BADARG  // Incorrect argument '%s' specified with command-line option '%s' 
  BADINP  // Tool cannot proceed further due to above errors in input files 
  NOCARG  // %s 
  ONPARM  // %s 
  LDFAIL  // Unable to load dynamic library %s:%s 
  LDLOOK  // Unable to locate startup routines in %s: %s 
  BBFAIL  // Unable to write to %s 
  FILOPE  // Unable to open "%s" for %s 
  BADTOP  // Unable to locate instance '%s' (specified by %s) in the design. This option will be ignored 
  NOTCMP  // Scope specified by -TOP '%s' is not a %s instance 
  TOOMNC  // More than one cell specified 
  BDARGF  // Command-line argument file '%s' could not be opened for reading (%s) 
  MISSCL  // Missing cell name for the build process 
  NOSNAP  // Snapshot '%s' does not exist in the libraries 
  NOWORK  // %s work library not found/defined 
  PRTSNP  // Design is partially elaborated. Connectivity information may not be complete 
  NOLICI  //  
  NOLICN  //  
  REARGF  // Command-line argument file '%s' included more than once 
  DUPARG  // Snapshot name provided by both ncverilog and the command-line. The snapshot name provided by command-line will be ignored 
  NOARGX  // Missing command-line argument file after -FILE option 
  BADCAT  // Category name '%s' is not recognized 
  REGEXB  // The naming convention pattern %s is not a legal regular expression 
  NOREGX  // The pattern parameter for message %s is null. Any name will match 
  BADRNG  // markSensListVarBits: ERROR -- range could not be determined for variable %s[%d:%d] 
  BADNAM  // %s: ERROR -- unsupported type '%s' 
  BDDUSP  // Badly formed design-unit specification %s 
  NLVSUF  // The hdl.var variable VERILOG_SUFFIX is defined, but is not a list 
  NOTEMP  // Cannot open/create temporary file '%s' for writing 
  CSTUDS  // Stack size has been limited 
  NOROOT  // Unable to locate Cadence installation root directory 
  NOHDLF  // No valid HDL source files provided 
  CNOTPR  // %s in file '%s' has multi-line comment, which does not end anywhere 
  COFILE  // Cannot open source file '%s' 
  MISAGO  // A '%s' option was found without an argument and will be ignored 
  NOSUPP  // HAL does not work in combination with 64-bit NC binaries 
  OBSOPT  //  
  UODIFW  // Unable to open design info file '%s' for writing 
  BLKERR  // Blackbox unit '%s' is not present in the design 
  LNTERR  //  
  NORUCY  // The argument '%s' in lint pragma does not map to any rule or category 
  PROTEC  // Protected design-unit '%s' encountered in the hierarchy and will not be processed by the tool 
  PLSNAP  // Snapshot '%s' does not exist (platform mismatch), rebuild 
  RVSNAP  // Snapshot '%s' does not exist (version mismatch), rebuild 
  SSNFND  // Snapshot '%s' does not exist in the libraries 
  SSNTRD  // %s not read 
  MULTOP  // The snapshot contains multiple top-level modules. Use the -TOP option to specify the hierarchy to be processed 
  AORAGG  // Array of record aggregates are not currently supported for arrays of unconstrained types. Remodel the design 
  AORCON  // Array of record created using concatenation of arrays of records is not supported. Remodel the design 
  BLKPAT  // Unsupported regular expression %s specified in blackbox file %s 
  DOMRNS  // Disable OOMR not supported 
  GBXERR  // Glassbox unit %s is not present in the design 
  IGNASR  // Expression creation error. The assertion/sequence/group in the module/design-unit %s will be ignored 
  IMPFNS  // Impure functions are not supported. The keyword impure will be ignored and the function will be treated as a pure function 
  INVASP  // Ignoring invalid enum encoding specification 
  INVCON  // Expression with invalid concatenation repeat count is being ignored 
  MOMRNS  // OOMR assignment to an element of a multi-dimensional array or a verilog memory is not supported. Remodel your design 
  NCDRNG  // In design-unit %s, unsupported non-constant discrete range is encountered 
  NMDINS  // Unable to find module for instance %s 
  NOBBFL  // Unable to open explicitly specified blackbox file for reading: %s 
  NOGBFL  // Unable to open explicitly specified glassbox file for reading: %s 
  NOCACC  // Design not compiled with connectivity access information. Pass -access +C flag to ncelab 
  NOFILO  // Unable to open file for writing %s 
  NOIDEN  // The actual parameter of the subprogram call on the formal part of the component instantiation statement is not an identifier 
  NOPATT  // Pre-defined attribute %s in design-unit %s is not synthesizable 
  NULRGW  // In design-unit/module %s, node %s has a null range defined. This node is being turned to dummy node because this design-unit/module is explicitly blackboxed 
  NULSTR  // Null strings are not supported 
  PERCIN  // The tool has encountered error(s) while processing instance %s. This instance will be ignored. 
  RNGEXP  // Type range has unsupported expressions. Only static constant expressions are allowed in the range 
  SHVUNS  // In design-unit %s, use of shared variables is not synthesizable 
  SOMRNE  // OOMR subprogram (function/task) call is not supported 
  SOMRNF  // OOMR subprogram (function/task) call is not supported 
  TOPERR  // The specified top-level instance: %s, is not present in the design 
  TOUTDE  // Design timed out after %s seconds 
  SUDPNS  // Modeling style of sequential UDP in module %s is not supported 
  UNHNDL  // Unhandled case in module/design-unit %s 
  UNKCIN  // Component instance is not fully bound (%s) 
  UNCINW  // Component instance is not fully bound (%s) 
  UNKGEN  // Design-unit/Module %s has Generic/Parameter of unsupported type 
  UNKLNG  // %s : Unknown language 
  UNKPEX  // addVerilogPortExpr : Unknown Port Expression %s 
  UNKWND  // findFormalType : Unknown node %s 
  UNSOMR  // OOMR on unsupported construct 
  UNSOPR  // Unsupported operator encountered %s. This expression will be ignored 
  UNSUPF  // An internal error occurred (may be due to an unsupported feature/function/operator): %s : %s 
  UNSVLG  // Unsupported Verilog 2001 feature: %s 
  USDUNT  // Unsupported design-unit %s encountered 
  USFDEC  // findFormalDecl: Unsupported call %s 
  USFENA  // Unsupported formal expression in named association 
  USRATR  // User-defined attribute in design-unit %s is not synthesizable 
  USRECR  // Recursive records are not supported 
  USTCOV  // In design-unit %s, type conversion %s is not supported 
  UUSCON  // Unsupported declaration/construct used. Cannot proceed further: %s 
  UUSTYP  // In design-unit %s, use of "%s" type is not synthesizable 
  WAVFRM  // Multiple waveform elements are not supported. Existing in %s %s, node %s 
  UNOMSU  // OOMR on function/task %s using nodes outside the subprogram scope is not supported 
  IGNCIN  // In %s '%s', initialization to node '%s' is ignored 
  CEVTNS  // Event on complex expression not supported. Complex expression %s in the event expression is replaced by %s, which is assigned the original complex expression 
  IGNCON  // Due to the above-mentioned error/warning, the design construct ( %s ) in which this error occurred will be ignored 
  FMLPDR  // Due to the above-mentioned error the formal port list of the %s is being dropped 
  NOSUBP  // Subprogram body not found 
  USENAR  // Array types using encoded enumeration type to specify range bounds are unsupported 
  USENRG  // Nodes of composite data types, having encoded enumeration type in array ranges is currently not supported 
  VHDRCE  // Race condition checks in HAL are supported for Verilog designs only, -RACES option is being ignored 
  BLDSTP  // Further processing stopped because of synthesizability errors 
  UNOPNF  // Unable to open %s file '%s' 
  PGMSSO  // The subprogram body of "%s" is under "synthesis_off/on" pragma 
  PGMCIG  // The design construct is under "synthesis_off/on" pragma. The semantics of the design may differ from simulation semantics 
  MULOPT  // The option %s has been specified multiple times on the command line. Only the first %d specification(s) will be considered 
  IPROTC  // Design contains protected HDL code. This tool does not analyze designs having protected HDL 
  PROTCT  // Ignoring instance '%s' as its module/design-unit is protected 
  TOPROE  // Design will not be analyzed because top-level module/design-unit is completely protected 
  NOSTAN  // The specified FSM cannot be analyzed for terminal and unreachable states 
  MIXGEN  // HAL does not support VHDL instantiation in a Verilog for-generate loop 
  UNSV2K  // The verilog-2001 construct : "%s" is not supported by the tool 
  SYSMOR  // Processing stopped because virtual memory limit exceeded 
  HALSIG  // Unable to proceed further due to a critical error. Contact Cadence Design Systems for resolution to this problem 
  CFESIG  // Unable to proceed further due to a critical error while processing %s '%s'. Contact Cadence Design Systems for resolution to this problem 
  SCPNFD  // Scope '%s' not found 
  PINNFD  // Pin '%s' not found in scope '%s' 
  MISVAL  // %s value not specified or is incorrect for pin '%s' in '%s' 
  NCDOMN  // Pin '%s' has '%s' specified as clock domain, but it is not specified as a clock or test clock 
  NOTSMD  // In scope '%s', pin '%s' set as 'logic_dbist', but not as test_mode pin 
  LOOPSZ  // Loop has more than %d iterations. Processing of loop may take some time, kindly wait 
  VLGMEM  // Module %s has Verilog memories. For large memories, processing may take some time 
  DISCAT  // The category '%s' in lint pragma attached to the above line, is disabled, which was earlier enabled 
  DISRUL  //  The rule '%s' in lint pragma attached to the above line, is disabled, which was earlier enabled 
  ENARUL  //  The rule '%s' in lint pragma attached to the above line, is enabled, which was earlier disabled 
  ENACAT  //  The category '%s' in lint pragma attached to the above line, is enabled, which was earlier disabled 
  NOCELL  // Cell corresponding to module '%s' is not found in synthesis library 
  UNLLIB  // Unable to load synthesis library '%s' 
  NOPORT  // No port is found in the design for pin '%s' in cell '%s' in synthesis library '%s' 
  NOPINL  // No pin is found in synthesis library '%s' for port '%s' of module/design-unit '%s' 
  NOCONW  // %s condition is not found for flip-flop/latch in the cell '%s' in synthesis library '%s' 
  NOCONF  // %s condition is not found for flip-flop/latch in the cell '%s' in synthesis library '%s' 
  UNSUOP  // Unable to determine the operator type in expression '%s' in cell '%s' in synthesis library '%s' 
  MAPLIB  // %s '%s' is mapped from library '%s' 
  FORGEN  // The instances in the given for-generate block will be unrolled %d times. Such processing takes time, kindly wait 
  GLSBOX  // %s %s automatically glassboxed 
  RULREP  // %s %s 
  SENNOT  // Test mode checks will not be performed as scan enable pin is not present in the design info file 
  UNKNRL  // Rule/message tag '%s' is not known to hal 
  STPUNK  // Definition file contains unknown rules. Either remove these rules or set parameter 'allow_only_hal_and_custom_rules' to 'no' 
  SYSIGN  // SystemVerilog '%s' construct is not supported by the tool. This will be ignored 
  SYSVIG  // SystemVerilog '%s' construct is not supported by the tool. This will be ignored 
  SYSVPS  // SystemVerilog construct: '%s' is not fully supported by HAL 
  BGOLAP  // Design-unit/Module '%s' specified for blackboxing overlaps with design-unit/module '%s' specified for glassboxing 
  LPNOFL  // -lps_verbose option will be ignored because -lps_cpf option is not specified 
}

category RMM "All checks complying to Reuse Methodology Manual" default_on
{
  CMBPAU {level="0"} // Combinational path detected through '%s' in module/design-unit '%s' 
  ASNCFL {level="0"} // Asynchronous feedback loop detected through set/reset of flip-flop(s) and '%s' in module/design-unit '%s' 
  GTDCLK {level="0"} // Clock gating detected for clock '%s' of flip-flop '%s' 
  LATINF {level="0"} // Process/always block models a latch, or signal '%s' is not assigned a value in all branches 
  MULMCK {level="1"} // Multiple master clocks found. Clock '%s' for flip-flop '%s' is derived from master input '%s' while the previously detected clocks were derived from '%s' for flip-flop '%s' 
  MRSTDT {level="1"} // Mix of synchronous and asynchronous set/reset found. Synchronous set/reset detected in '%s' and asynchronous set/reset detected in '%s' 
  TPOUNR {level="1"} // Output '%s' of top-level module is not a register 
  MISSEL {level="1"} // Signal '%s' missing from sensitivity list of a sequential process/block 
  USESEL {level="1"} // Signal '%s' should not be used in the sensitivity list of a sequential process/block 
  CBYNAM {level="1"} // Port connections for instance '%s' of %s '%s' should be made by name rather than by positional ordered list 
  NOTECH {level="1"} // Instance '%s' is instantiating a technology cell. Avoid using technology cells in the design 
  DIFCLK {level="2"} // Clock '%s' is being renamed to '%s' 
  DIFRST {level="2"} // Set/Reset '%s' is being renamed to '%s' 
  VERCAS {level="2"} // Identifier, label, instance, or module name '%s' reused with a case difference 
  DIRRNG {level="2"} // Inconsistent ordering of bits in range declarations -- should be all %s ranges 
  KYEDIF {level="2"} // EDIF reserved word '%s' used as an identifier or label 
  STYVAL {level="3"} // Numeric value '%d' used for identifier '%s'. Use constants to avoid portability issues 
  STYBLK {level="3"} // Block statement used. This will create portability issues 
  VHDREP {level="3"} // Repeated usage of identifier or label name '%s' 
  VERREP {level="3"} // Repeated usage of identifier or label name '%s' 
  MULTMF {level="3"} // More than one design-unit definition in file '%s' 
  KEYWOD {level="3"} // VHDL reserved word '%s' used as an identifier or label 
  KVHWOD {level="3"} // Verilog reserved word '%s' used as an identifier or label 
  STYSUL {level="3"} // Type std_ulogic used for identifier '%s'. Use std_logic to avoid portability issues 
  STYSUV {level="3"} // Type std_ulogic vector used for identifier '%s'. Use std_logic_vector to avoid portability issues 
  STYBIT {level="3"} // Type bit used for identifier '%s'. Use std_logic to avoid portability issues 
  STYBTV {level="3"} // Type bit_vector used for identifier '%s'. Use std_logic_vector to avoid portability issues 
  CKEYWD {level="3"} // C/C++ reserved word '%s' used as an identifier or label 
  UPCLBL {level="4"} // Label '%s' should be written in uppercase 
  DIFFMN {level="4"} // %s name '%s' differs from file name '%s' 
  NOBLKN {level="4"} // Each block should be labeled with a meaningful name 
  SEPLIN {level="4"} // Use a separate line for each HDL statement 
  NOINSN {level="4"} // Each module/gate/primitive instance should be labeled with a meaningful name 
  LCVARN {level="4"} // %s name '%s' uses uppercase characters 
  UCCONN {level="4"} // Lowercase characters used for identifier '%s'. Use uppercase characters for names of constants and user-defined types 
  ACNCPI {level="0"} // Asynchronous %s '%s' of latch/flip-flop '%s' is not controllable from primary inputs 
  ATLGLC {level="1"} // Glue logic inferred in top-level module/design-unit '%s' 
  SYNSCU {level="3"} // Embedded synthesis script used in the design 
}

category LOW_POWER "All checks related to low power design" default_on
{
  SRENSL {level="0"} // State retention element/cell '%s' is not inferred as a flip-flop. It is %s 
  SRPDDC {level="1"} // Retention flip-flops in the power domain '%s' are controlled by different %s 
  ISPDDC {level="1"} // Isolation rules from power domain '%s' are controlled by different control pins 
  LPISCS {level="1"} // The isolation controlling signal '%s' is not an output of a module or primary input 
  LPSRCS {level="1"} // The %s edge signal '%s' is not an output of a module or primary input 
  LOW_POWER_SYNTH       // All checks related to low power due to synthesizability errors
}

category LOW_POWER_SYNTH "All checks related to low power due to synthesizability errors" default_on
{
  CNREAL {level="1"} // Real variable %s is used in %s %s. Real variables are not synthesizable 
  GRDASN {level="0"} // In design-unit %s, non-synthesizable guarded assignments are encountered 
  INIMEM {level="2"} // Initialization of memory %s in module %s is ignored 
  INITBI  // Initial block in primitive is ignored 
  FINUSP {level="2"} // Module '%s' has a final block, which is ignored by synthesis tools 
  INIUSP {level="2"} // %s %s has an initial block or a variable declaration assignment, which is ignored by synthesis tools 
  LATINF {level="0"} // Process/always block models a latch, or signal '%s' is not assigned a value in all branches 
  FNAVPC {level="1"} // Function %s 
  COMBLP {level="1"} // In %s %s, combinational loop detected for node %s 
  CMBPAU {level="0"} // Combinational path detected through '%s' in module/design-unit '%s' 
  CBPAHI {level="2"} // Combinatorial path crossing multiple units drives '%s' 
  IGNDLY {level="2"} // Lumped delay in %s '%s' is ignored 
}


    // ---------------- //
    //  HAL Parameters  //
    // ---------------- //


params HAL {allow_error_suppression="yes"}
// params HAL {allow_error_suppression="no"}
// params HAL {allow_error_suppression="yes"}

params HAL {allow_intern_gen_sync_reset="no"}
params HAL {allow_only_hal_and_custom_rules="no"}
params HAL {check_verilog_reg_as_vhdl_var="no"}
params HAL {clock_list="APPEND"}
// params HAL {clock_list="append"}
// params HAL {clock_list="overwrite"}

params HAL {code_comment_style_verilog="single-line"}
params HAL {controllability_observability_threshold="15"}
params HAL {convention_for_control_type="mixed"}
params HAL {convention_for_set_reset_style="asynchronous"}
params HAL {disable_unclassified_rules="yes"}
// params HAL {disable_unclassified_rules="no"}
// params HAL {disable_unclassified_rules="yes"}

params HAL {display_rule_control="no"}
// params HAL {display_rule_control="no"}
// params HAL {display_rule_control="yes"}

params HAL {divided_clock_domain_same_as_master="yes"}
params HAL {gated_clock_domain_same_as_master="no"}
params HAL {header_case_sensitive="no"}
params HAL {header_field_separator=":"}
params HAL {header_section_separator="-"}
params HAL {ignore_empty_line_for_comment="no"}
params HAL {internally_generated_clock_as_clock="no"}
params HAL {issue_noblkn="both"}
params HAL {pragma_control="strict"}
params HAL {preserve_unused_elements="no"}
params HAL {regex_style="csh"}
// params HAL {regex_style="csh"}
// params HAL {regex_style="full"}

params HAL {severity_downgradable="no"}
// params HAL {severity_downgradable="no"}
// params HAL {severity_downgradable="yes"}

params HAL {suppress_synthesizability_errors="no"}
params HAL {unsized_literal="size_as_per_type"}


    // ----------------------- //
    //  Rule Severity Changes  //
    // ----------------------- //

params UNRCHS {ERROR}
params WAITML {ERROR}
params AWNDEL {ERROR}
params TERMST {ERROR}
params OUTRNG {ERROR}
params TOPGEN {ERROR}

    // ----------------- //
    //  Rule Parameters  //
    // ----------------- //

params TSBNTH {mask_cell_hierarchical="yes"}
params TSBNTH {mask_cells="and:nand:mux"}
params PBYNAM {num_params="5"}
params LDFFPI {logic_depth_adder="1"}
params LDFFPI {logic_depth_and="1"}
params LDFFPI {logic_depth_divide="1"}
params LDFFPI {logic_depth_inverter="1"}
params LDFFPI {logic_depth_multiply="1"}
params LDFFPI {logic_depth_mux="1"}
params LDFFPI {logic_depth_nand="1"}
params LDFFPI {logic_depth_nor="1"}
params LDFFPI {logic_depth_or="1"}
params LDFFPI {logic_depth_reference="1"}
params LDFFPI {logic_depth_subtract="1"}
params LDFFPI {logic_depth_threshold="10"}
params LDFFPI {logic_depth_xnor="1"}
params LDFFPI {logic_depth_xor="1"}
params IDLENG {exception_list=""}
params IDLENG {max_length="16"}
params IDLENG {min_length="4"}
params SVIFNM {pattern="*_bus"}
params SVIFNM {text=": should end with '_bus'"}
params NULCSE {allow_vhdl_two_state_logic="no"}
params MPCMPE {expression_complexity="5"}
params COMEND {min_line_count="0"}
params SIGLNM {pattern="*"}
params SIGLNM {text=""}
params RECTYP {allow_record_declaration="yes"}
params TIELOG {output_testing_mode="relax"}
params LOOPTM {max_operation="10"}
params RENAME {check_part_select_rename="disallow"}
params DFDRVS {ff_latch_set_reset_check="yes"}
params RSTNAM {local_regex_style="full"}
// params RSTNAM {local_regex_style="csh"}
// params RSTNAM {local_regex_style="full"}

params RSTNAM {pattern="_rst$|^rst_|^rst$"}
params RSTNAM {text=": should end with '_rst' or start with 'rst_' or just be 'rst'"}
params MEMRNM {pattern="*_mem"}
params MEMRNM {text=": should end with '_mem'"}
params REGRNM {pattern="*"}
params REGRNM {text=""}
params WIRENM {pattern="*"}
params WIRENM {text=""}
params SNCRST {sync_reset_style="either"}
params CTLCHR {off}
// params CTLCHR {off}
// params CTLCHR {on}

params DESULN {max_lines="400"}
params PCKGNM {pattern="*_pkg"}
params PCKGNM {text=": should end with '_pkg'"}
params LOCVNM {pattern="^l_.*$"}
params LOCVNM {text=": should start with 'l_'"}
params INSTNM {pattern="*"}
params INSTNM {text=""}
params ARCHID {local_regex_style="full"}
// params ARCHID {local_regex_style="csh"}
// params ARCHID {local_regex_style="full"}

params ARCHID {suffix_list="rtl|^rtl_|_rtl$|beh|^beh_|_beh$|syn|^syn_|_syn$|ppr|^ppr_|_ppr$|logic|^logic_|_logic$|hls|^hls_|_hls$|vit|^vit_|_vit$|tst|^tst_|_tst$"}
params KEYWOD {off}
// params KEYWOD {off}
// params KEYWOD {on}

params ASUMNM {pattern="^assume_.*$"}
params ASUMNM {text=": should start with 'assume_'"}
params EXTFSM {allow_fsm_output="yes"}
params ARCHNM {pattern="*_arch"}
params ARCHNM {text=": should end with '_arch'"}
params HIMPNM {pattern="*_z"}
params HIMPNM {text=": should end with '_z'"}
params RGOPNM {pattern="*_reg"}
params RGOPNM {text=": should end with '_reg'"}
params BEH_ARCHNM {pattern="^(TB|SIM|BEH)"}
params BEH_ARCHNM {text=""}
params PRTODR {layout_order=""}
params BLKLNM {pattern="*_blk"}
params BLKLNM {text=": should end with '_blk'"}
params DIFSIG {pattern="*"}
params CBYNAM {check_tech_cells="yes"}
params NTACHR {local_regex_style="full"}
// params NTACHR {local_regex_style="csh"}
// params NTACHR {local_regex_style="full"}

params NTACHR {pattern="^([_]?([a-zA-Z0-9:]+_?[a-zA-Z0-9:]*)*)$"}
params NTACHR {reserved_keyword_list=""}
params NTACHR {text=""}
params FILSUF {local_regex_style="full"}
// params FILSUF {local_regex_style="csh"}
// params FILSUF {local_regex_style="full"}

params FILSUF {pattern="(vhd$|vhdl$|v$|cpp$|cxx$|c++$|cc$|c$)"}
params POIASG {ignore_poiasg="no"}
params CLKSNM {pattern="*_CK"}
params CLKSNM {text=": should end with '_CK'"}
params NOINCD {mode="relax"}
params SUBPLN {max_lines="300"}
params NETDCL {Constant_Section_Ordering="no_order"}
params NETDCL {IO_Decl_Section_Ordering="no_order"}
params NETDCL {Internal_Signal_Section_Ordering="no_order"}
params COVRNM {pattern="^cover_.*$"}
params COVRNM {text=": should start with 'cover_'"}
params OUTPNM {pattern="*_O"}
params OUTPNM {text=": should end with '_O'"}
params MEMNOP {output_bypass_mode="strict"}
params INSTLB {max_length="8"}
params CMPPKG {pattern="*_cmp_pkg"}
params CMPPKG {text=": should end with '_cmp_pkg'"}
params RTL_ARCHNM {pattern="^(RTL|STR)"}
params RTL_ARCHNM {text=""}
params LENCPI {controllable_thru_comb_logic="no"}
params RULREP {report_successfull="yes"}
params RULREP {report_unchecked="yes"}
params RULREP {report_unclassified="no"}
params RULREP {report_violated="yes"}
params LOGNEG {mode="strict"}
params ASNRST {async_reset_style="active_low"}
params SUBRNM {pattern="*_proc"}
params SUBRNM {text=": should end with '_proc'"}
params EXPIPC {allow_concat_operation="no"}
params LIBRNM {pattern="*"}
params LIBRNM {text=""}
params ASRTSC {controllable_thru_comb_logic="no"}
params MULNBA {mulnba_reset_mode="no"}
params MODLNM {pattern="*_mod"}
params MODLNM {text=": should end with '_mod'"}
params MODLNM {top_only="no"}
params EDGMIX {hierarchical="no"}
params ALOWNM {local_regex_style="full"}
// params ALOWNM {local_regex_style="csh"}
// params ALOWNM {local_regex_style="full"}

params ALOWNM {pattern=".*(VSS|VDD|GND|VCC).*|.*(vss|vdd|gnd|vcc).*"}
params ALOWNM {text=""}
params LMTSTS {max_states="40"}
params DIFRST {setreset_type="async_and_sync"}
params LTCHNM {issue_for_ports="yes"}
params LTCHNM {pattern="*_l"}
params LTCHNM {text=": should end with '_l'"}
params ALOWID {pattern="*_n"}
params ALOWID {text=": should end with '_n'"}
params VARLNM {pattern="*"}
params VARLNM {text=""}
params UNCONO {check_on_std_cells="yes"}
params UNCONO {ignore_explicitly_unconnected_port="no"}
params UNCONO {ignore_port_with_no_load="no"}
params UNCONN {allow_explicitly_unconnected="no"}
// params UNCONN {allow_explicitly_unconnected="no"}
// params UNCONN {allow_explicitly_unconnected="yes"}

params UNCONI {ignore_explicitly_unconnected_port="no"}
params UNCONI {ignore_port_with_no_load="no"}
params FILENM {pattern="*_F"}
params FILENM {text=": should end with '_F'"}
params PRTLYO {layout_order=""}
params INSYNC {ff_sync_combi_logic_ok="yes"}
params INSYNC {ff_sync_mixed_clock_edge_ok="no"}
params INSYNC {lockup_latch_sync_allowed="yes"}
params INTGNM {pattern="*"}
params INTGNM {text=""}
params MULSNO {order=""}
params IGNDLY {allow_delay_in_ff_data="no"}
params FSMIDN {fsm_states_in_default_clause="no"}
params DIRRNG {direction="descending"}
// params DIRRNG {direction="ascending"}
// params DIRRNG {direction="descending"}

params MAXLEN {off}
// params MAXLEN {off}
// params MAXLEN {on}

params MAXLEN {max_line_length="80"}
params TESTNM {pattern="*_test"}
params TESTNM {text=": should end with '_test'"}
params SIGLEN {exception_list=""}
params SIGLEN {max_length="32"}
params SIGLEN {min_length="1"}
params TRUNCZ {off}
// params TRUNCZ {off}
// params TRUNCZ {on}

params TXCNOP {output_bypass_mode="strict"}
params REALNM {pattern="*"}
params REALNM {text=""}
params TASKNM {pattern="task*"}
params TASKNM {text=": should start with 'task'"}
params CNSTLT {vhdl_multibit_null_literal="disallow"}
params CNSTLT {vlog_multibit_null_literal="allow"}
params FUNCNM {pattern="func*"}
params FUNCNM {text=": should start with 'func'"}
params PROPNM {pattern="^p_.*$"}
params PROPNM {text=": should start with 'p_'"}
params MXPROC {max_processes="10"}
params INPTNM {pattern="*_I"}
params INPTNM {text=": should end with '_I'"}
params PORTNM {pattern="*"}
params PORTNM {text=""}
params PORTNM {top_only="no"}
params ASTMNM {pattern="^assert_.*$"}
params ASTMNM {text=": should start with 'assert_'"}
params CBPAHI {report_path_till_top_level="no"}
params CBPAHI {report_paths="all"}
// params CBPAHI {report_paths="all"}
// params CBPAHI {report_paths="nocell"}

params TBCHNM {pattern="$MODNAME"}
params CDEFNC {case_default_specification="relax"}
params CDEFNC {combinational_block_only="no"}
params CDEFNC {full_case_with_no_default_allowed="yes"}
params MAXPRT {max_ports="25"}
params UELOPR {ignore_addition="no"}
params UELOPR {ignore_subtraction="no"}
params STMCNM {pattern="*_state"}
params STMCNM {text=": should end with '_state'"}
params PARMNM {pattern="*"}
params PARMNM {text=""}
params SEQNNM {pattern="^s_.*$"}
params SEQNNM {text=": should start with 's_'"}
params ACCSNM {pattern="*_P"}
params ACCSNM {text=": should end with '_P'"}
params ENTYNM {pattern="*_ent"}
params ENTYNM {text=": should end with '_ent'"}
params SLENEX {scanlengthlimit="200"}
params NUMSUF {vector_only="yes"}
params TBNNAM {pattern="*_tb"}
params TBNNAM {text=": should end with '_tb'"}
params CNSTNM {pattern="*_C"}
params CNSTNM {text=": should end with '_C'"}
params SYNASN {asynchronous_reset_is_synchronous="yes"}
params CLKDMN {delayed_clock_as_clock="no"}
params UCOPNM {pattern="*_nc"}
params UCOPNM {text=": should end with '_nc'"}
params BOUINC {lower_bound="0"}
params LMULOP {multiplication_result_limit="64"}
params MXTSBC {max_tri_state_buff_connect_limit="5"}
params MLITNU {max_literals="20"}
params CONFNM {local_regex_style="full"}
// params CONFNM {local_regex_style="csh"}
// params CONFNM {local_regex_style="full"}

params CONFNM {pattern="^$ENTNAME.*$"}
params CONFNM {text=": should start with the name of the entity to which configuration is bound"}
params NOBLKN {check_nested_blocks="no"}
params NOBLKN {off}
// params NOBLKN {off}
// params NOBLKN {on}

params FFCSTD {output_of_blackbox="variable"}
params FFCSTD {output_of_latch="variable"}
params MULTCK {flipflop_reporting_limit="10"}
params MULBAS {mulbas_quick_check="yes"}
params IOPTNM {pattern="*_IO"}
params IOPTNM {text=": should end with '_IO'"}
params VLFLNM {pattern="$MODNAME"}

    // --------------- //
    //  Rule Renaming  //
    // --------------- //