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// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct  4 19:58:22 MDT 2017
// Date        : Fri Jan 26 22:39:31 2018
// Host        : Ateana3 running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode synth_stub
//               C:/Cores5/FT64/FT64/FT64.srcs/sources_1/ip/NexysVideoClkgen/NexysVideoClkgen_stub.v
// Design      : NexysVideoClkgen
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7a200tsbg484-1
// --------------------------------------------------------------------------------
 
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module NexysVideoClkgen(clk100, clk400, clk80, clk50, clk200, reset, locked, 
  clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk100,clk400,clk80,clk50,clk200,reset,locked,clk_in1" */;
  output clk100;
  output clk400;
  output clk80;
  output clk50;
  output clk200;
  input reset;
  output locked;
  input clk_in1;
endmodule