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[/] [timerocd/] [trunk/] [src/] [testbench/] [TimerOCD_testbench.vhd] - Rev 2
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-------------------------------------------------------------------------------- -- File name : TimerOCD_testbench.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2015 Donna Whisnant/Dewtronics. -- Contact: http://www.dewtronics.com/ -- -- This file may be used under the terms of the GNU Lesser General Public License -- version 3.0 as published by the Free Software Foundation and appearing -- in the files lgpl-3.0.txt/gpl-3.0.txt included in the packaging of this file. -- Please review the following information to ensure the GNU Lesser General -- Public License version 3.0 requirements will be met: -- https://www.gnu.org/licenses/lgpl-3.0.html -- Attribution requested, but not required. -- -- Target Device: Xilinx Spartan-6 XC6SLX9-2-TQG144 -- Using Numato Mimas Spartan 6 FPGA Development Board -- http://numato.com/mimas-spartan-6-fpga-development-board.html -- -- -- Timer Output Compare Driver Test Bench -- -------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use std.textio.all; use IEEE.std_logic_textio.all; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- entity TimerOCD_testbench is end TimerOCD_testbench; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- architecture behavior of TimerOCD_testbench is constant timerocd_numTimers : INTEGER := 64; -- Number of Timers Supported constant timerocd_numTimerBits: INTEGER := 6; -- Number of Timer Address Bits constant timerocd_numXferBits: INTEGER := 64; -- Number of bits transmitted/received during SPI data exchange constant timerocd_numOutputs: INTEGER := 2; -- Number of Outputs Supported signal timerocd_reset_n: STD_LOGIC := '0'; -- Master reset (Active Low) signal timerocd_SPI_SS_n: STD_LOGIC := '1'; -- SPI Slave Select In (Active Low) signal timerocd_SPI_CLK: STD_LOGIC := '0'; -- SPI Clock In signal timerocd_SPI_MOSI: STD_LOGIC := '0'; -- SPI Master Out, Slave In signal timerocd_SPI_MISO: STD_LOGIC; -- SPI Master In, Slave Out signal timerocd_FiberOut: STD_LOGIC_VECTOR(timerocd_numOutputs-1 downto 0); -- Fiber Output Drive Outputs signal timerocd_GCLK_in: STD_LOGIC := '0'; -- Master System Clock (GCLK) on Numato Mimas Spartan6 Module signal timerocd_SW: STD_LOGIC_VECTOR(3 downto 0) := (OTHERS => '1'); -- Push Buttons signal timerocd_LED: STD_LOGIC_VECTOR(7 downto 0); -- LEDs subtype TTimerAddr is STD_LOGIC_VECTOR(timerocd_numTimerBits-1 downto 0); subtype TNote is STD_LOGIC_VECTOR(6 downto 0); subtype TPower is STD_LOGIC_VECTOR(6 downto 0); subtype TPitchBend is STD_LOGIC_VECTOR(13 downto 0); -- Constant Definitions for test: constant spiclk_period : time := 125 ns; -- AVR will be using CK/2 or 16MHz/2 or 8MHz for the SPI clock (STM32F4 will likely use 5.25MHz or 10.5MHz) constant gclk_period : time := 10 ns; -- Master System Clock (GCLK) on Numato Mimas Spartan6 Module is 100MHz -- constant spiclk_period_hi : time := spiclk_period/5; -- Used for simulation to provide non-symmetric clock pulses -- constant spiclk_period_lo : time := (4*spiclk_period/5); constant spiclk_period_hi : time := spiclk_period/2; constant spiclk_period_lo : time := spiclk_period/2; constant spiclk_period_dly : time := 2 us; -- Conversion Functions: function mkTimer(constant nTimer : INTEGER) return TTimerAddr is begin return CONV_STD_LOGIC_VECTOR(nTimer, timerocd_numTimerBits); end function mkTimer; function mkNote(constant nNote : INTEGER) return TNote is begin return CONV_STD_LOGIC_VECTOR(nNote, 7); end function mkNote; function mkPower(constant nPower : INTEGER) return TPower is begin return CONV_STD_LOGIC_VECTOR(nPower, 7); end function mkPower; function mkPitchBend(constant nPitchBend : INTEGER) return TPitchBend is begin return CONV_STD_LOGIC_VECTOR(nPitchBend, 14); end function mkPitchBend; -- -------------------------------------------------------------------- -- printLED: -- This procedure prints LED debug string -- -------------------------------------------------------------------- procedure printLED(constant nLED : in STD_LOGIC_VECTOR(7 downto 0)) is variable lineTemp : line; begin write(lineTemp, string'("LEDs: ")); write(lineTemp, nLED, LEFT, 8); writeline(output, lineTemp); end procedure printLED; -- -------------------------------------------------------------------- -- printSW: -- This procedure prints SW debug string -- -------------------------------------------------------------------- procedure printSW(constant nSW : in STD_LOGIC_VECTOR(3 downto 0)) is variable lineTemp : line; begin write(lineTemp, string'("Switches: ")); write(lineTemp, nSW, LEFT, 4); writeline(output, lineTemp); end procedure printSW; -- -------------------------------------------------------------------- -- writeSPI: -- This procedure will write a single byte to the SPI port -- -------------------------------------------------------------------- procedure writeSPI( constant nByte : in STD_LOGIC_VECTOR(7 downto 0); signal MOSI : out STD_LOGIC; signal CLK : out STD_LOGIC) is begin for i in 7 downto 0 loop MOSI <= nByte(i); wait for spiclk_period_lo/2; CLK <= '1'; wait for spiclk_period_hi/2; CLK <= '0'; end loop; end procedure writeSPI; -- -------------------------------------------------------------------- -- readSPI: -- This procedure will read a single byte from the SPI port -- -------------------------------------------------------------------- procedure readSPI( variable nByte : out STD_LOGIC_VECTOR(7 downto 0); signal MISO : in STD_LOGIC; signal MOSI : out STD_LOGIC; signal CLK : out STD_LOGIC) is begin MOSI <= '0'; for i in 7 downto 0 loop wait for spiclk_period_lo/2; CLK <= '1'; wait for spiclk_period_hi/2; CLK <= '0'; nByte(i) := MISO; end loop; end procedure readSPI; -- -------------------------------------------------------------------- -- readWriteSPI: -- This procedure will read a single byte from the SPI port while -- writing a new byte -- -------------------------------------------------------------------- procedure readWriteSPI( constant nByteToWrite : in STD_LOGIC_VECTOR(7 downto 0); variable nByteRead : out STD_LOGIC_VECTOR(7 downto 0); signal MISO : in STD_LOGIC; signal MOSI : out STD_LOGIC; signal CLK : out STD_LOGIC) is begin for i in 7 downto 0 loop MOSI <= nByteToWrite(i); wait for spiclk_period_lo/2; CLK <= '1'; wait for spiclk_period_hi/2; CLK <= '0'; nByteRead(i) := MISO; end loop; end procedure readWriteSPI; -- -------------------------------------------------------------------- -- writeCommand: -- This procedure will write a command to the device -- -------------------------------------------------------------------- procedure writeCommand( constant nCommand : in STD_LOGIC_VECTOR(5 downto 0); variable nCmdData : out STD_LOGIC_VECTOR(3 downto 0); signal SS : out STD_LOGIC; signal MISO : in STD_LOGIC; signal MOSI : out STD_LOGIC; signal CLK : out STD_LOGIC) is variable nReceivedByte : STD_LOGIC_VECTOR(7 downto 0); begin SS <= '0'; wait for spiclk_period_dly/2; readWriteSPI(nByteToWrite => "01" & nCommand, -- Send Write Command nByteRead => nReceivedByte, MISO => MISO, MOSI => MOSI, CLK => CLK); wait for spiclk_period_dly/2; MOSI <= '0'; SS <= '1'; wait for spiclk_period_dly/2; nCmdData := nReceivedByte(3 downto 0); end procedure writeCommand; -- -------------------------------------------------------------------- -- readCommand: -- This procedure will send a readcommand to the device -- -------------------------------------------------------------------- procedure readCommand( constant nCommand : in STD_LOGIC_VECTOR(5 downto 0); variable nCmdData : out STD_LOGIC_VECTOR(3 downto 0); signal SS : out STD_LOGIC; signal MISO : in STD_LOGIC; signal MOSI : out STD_LOGIC; signal CLK : out STD_LOGIC) is variable nReceivedByte : STD_LOGIC_VECTOR(7 downto 0); begin SS <= '0'; wait for spiclk_period_dly/2; readWriteSPI(nByteToWrite => "11" & nCommand, -- Send Read Command nByteRead => nReceivedByte, MISO => MISO, MOSI => MOSI, CLK => CLK); wait for spiclk_period_dly/2; MOSI <= '0'; SS <= '1'; wait for spiclk_period_dly/2; nCmdData := nReceivedByte(3 downto 0); end procedure readCommand; -- -------------------------------------------------------------------- -- writeTimerOC: -- This procedure will write a Timer Note pair to the specified -- Timer OC -- -------------------------------------------------------------------- procedure writeTimerOC( constant nTimer : in TTimerAddr; constant nNoteLeft : in TNote; constant nPowerLeft : in TPower; constant nPitchBendLeft : in TPitchBend; constant nNoteRight : in TNote; constant nPowerRight : in TPower; constant nPitchBendRight : in TPitchBend; signal SS : out STD_LOGIC; signal MOSI : out STD_LOGIC; signal CLK : out STD_LOGIC) is begin SS <= '0'; wait for spiclk_period_dly/2; writeSPI(nByte => "00" & nTimer, -- Send Write Address for the specified output and timer MOSI => MOSI, CLK => CLK); WriteSPI(nByte => "0" & nNoteLeft, -- Send Left Note MOSI => MOSI, CLK => CLK); WriteSPI(nByte => "0" & nPowerLeft, MOSI => MOSI, CLK => CLK); WriteSPI(nByte => "00" & nPitchBendLeft(13 downto 8), MOSI => MOSI, CLK => CLK); WriteSPI(nByte => nPitchBendLeft(7 downto 0), MOSI => MOSI, CLK => CLK); WriteSPI(nByte => "0" & nNoteRight, -- Send Right Note MOSI => MOSI, CLK => CLK); WriteSPI(nByte => "0" & nPowerRight, MOSI => MOSI, CLK => CLK); WriteSPI(nByte => "00" & nPitchBendRight(13 downto 8), MOSI => MOSI, CLK => CLK); WriteSPI(nByte => nPitchBendRight(7 downto 0), MOSI => MOSI, CLK => CLK); wait for spiclk_period_dly/2; MOSI <= '0'; SS <= '1'; wait for spiclk_period_dly/2; end procedure writeTimerOC; -- -------------------------------------------------------------------- -- readTimerOC: -- This procedure will read a Timer Note pair from the specified -- Timer OC -- -------------------------------------------------------------------- procedure readTimerOC( constant nTimer : in TTimerAddr; variable nRetVal : out STD_LOGIC_VECTOR(timerocd_numXferBits-1 downto 0); signal SS : out STD_LOGIC; signal MISO : in STD_LOGIC; signal MOSI : out STD_LOGIC; signal CLK : out STD_LOGIC) is begin SS <= '0'; wait for spiclk_period_dly/2; writeSPI(nByte => "10" & nTimer, -- Send Read Address for the specified output and timer MOSI => MOSI, CLK => CLK); for i in ((timerocd_numXferBits-1)/8)+1 downto 1 loop readSPI(nRetVal((i*8-1) downto ((i-1)*8)), MISO => MISO, MOSI => MOSI, CLK => CLK); end loop; wait for spiclk_period_dly/2; SS <= '1'; wait for spiclk_period_dly/2; end procedure readTimerOC; -- -------------------------------------------------------------------- -- readWriteTimerOC: -- This procedure will read a Timer Note pair from the specified -- Timer OC while writing a new Timer Note pair -- -------------------------------------------------------------------- procedure readWriteTimerOC( constant nTimer : in TTimerAddr; constant nNoteLeft : in TNote; constant nPowerLeft : in TPower; constant nPitchBendLeft : in TPitchBend; constant nNoteRight : in TNote; constant nPowerRight : in TPower; constant nPitchBendRight : in TPitchBend; variable nRetVal : out STD_LOGIC_VECTOR(timerocd_numXferBits-1 downto 0); signal SS : out STD_LOGIC; signal MISO : in STD_LOGIC; signal MOSI : out STD_LOGIC; signal CLK : out STD_LOGIC) is begin SS <= '0'; wait for spiclk_period_dly/2; writeSPI(nByte => "00" & nTimer, -- Send Read/Write Address for the specified output and timer MOSI => MOSI, CLK => CLK); readwriteSPI(nByteToWrite => "0" & nNoteLeft, -- Send Left Note nByteRead => nRetVal(63 downto 56), MISO => MISO, MOSI => MOSI, CLK => CLK); readwriteSPI(nByteToWrite => "0" & nPowerLeft, nByteRead => nRetVal(55 downto 48), MISO => MISO, MOSI => MOSI, CLK => CLK); readwriteSPI(nByteToWrite => "00" & nPitchBendLeft(13 downto 8), nByteRead => nRetVal(47 downto 40), MISO => MISO, MOSI => MOSI, CLK => CLK); readwriteSPI(nByteToWrite => nPitchBendLeft(7 downto 0), nByteRead => nRetVal(39 downto 32), MISO => MISO, MOSI => MOSI, CLK => CLK); readwriteSPI(nByteToWrite => "0" & nNoteRight, -- Send Right Note nByteRead => nRetVal(31 downto 24), MISO => MISO, MOSI => MOSI, CLK => CLK); readwriteSPI(nByteToWrite => "0" & nPowerRight, nByteRead => nRetVal(23 downto 16), MISO => MISO, MOSI => MOSI, CLK => CLK); readwriteSPI(nByteToWrite => "00" & nPitchBendRight(13 downto 8), nByteRead => nRetVal(15 downto 8), MISO => MISO, MOSI => MOSI, CLK => CLK); readwriteSPI(nByteToWrite => nPitchBendRight(7 downto 0), nByteRead => nRetVal(7 downto 0), MISO => MISO, MOSI => MOSI, CLK => CLK); wait for spiclk_period_dly/2; MOSI <= '0'; SS <= '1'; end procedure readWriteTimerOC; begin -- Instantiate TimerOCD UUT (Unit Under Test): uut : entity work.TimerOCD port map ( reset_n => timerocd_reset_n, SPI_SS_n_in => timerocd_SPI_SS_n, SPI_CLK_in => timerocd_SPI_CLK, SPI_MOSI_in => timerocd_SPI_MOSI, SPI_MISO => timerocd_SPI_MISO, FiberOut => timerocd_FiberOut, GCLK_in => timerocd_GCLK_in, SW0 => timerocd_SW(0), SW1 => timerocd_SW(1), SW2 => timerocd_SW(2), SW3 => timerocd_SW(3), LED => timerocd_LED ); -- -------------------------------------------------------------------- -- gclkproc: -- This process generates the free-running master GCLK clock for -- the FPGA -- -------------------------------------------------------------------- gclkproc : process begin timerocd_GCLK_in <= '0'; wait for gclk_period/2; timerocd_GCLK_in <= '1'; wait for gclk_period/2; end process gclkproc; -- -------------------------------------------------------------------- -- stimproc: -- Stimulus Process -- -------------------------------------------------------------------- stimproc : process variable nReceivedData : STD_LOGIC_VECTOR(timerocd_numXferBits-1 downto 0) := (OTHERS => '0'); variable nRcvCmdData : STD_LOGIC_VECTOR(3 downto 0); variable lineTemp : line; begin -- System Reset: timerocd_reset_n <= '0'; wait for 3 ms; timerocd_reset_n <= '1'; wait for 30 us; -- At 100MHz GCLK, TimerOCD takes about 20.5uS to complete reset processing after reset signal goes high. Allow 30uS to be safe. writeTimerOC(nTimer => mkTimer(0), nNoteLeft => mkNote(21), nPowerLeft => mkPower(1), nPitchBendLeft => mkPitchBend(16#2000#), nNoteRight => mkNote(0), nPowerRight => mkPower(0), nPitchBendRight => mkPitchBend(16#2000#), SS => timerocd_SPI_SS_n, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Writing Bank 0 Timer 0 = 15012000 | 00002000")); writeline(output, lineTemp); wait for 5 ms; report "Switching to Bank 2"; writeCommand(nCommand => "000110", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); assert (nRcvCmdData = "0000") report "Expected Current Data: 0000" severity warning; write(lineTemp, string'("Writing Bank 2 Timer 2 = 6A553000 | 00002000")); writeline(output, lineTemp); writeTimerOC(nTimer => mkTimer(2), nNoteLeft => mkNote(106), nPowerLeft => mkPower(85), nPitchBendLeft => mkPitchBend(16#3000#), nNoteRight => mkNote(0), nPowerRight => mkPower(0), nPitchBendRight => mkPitchBend(16#2000#), SS => timerocd_SPI_SS_n, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); wait for 5 ms; report "Switching to Bank 3"; writeCommand(nCommand => "000111", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); assert (nRcvCmdData = "0010") report "Expected Current Data: 0010" severity warning; writeTimerOC(nTimer => mkTimer(3), nNoteLeft => mkNote(0), nPowerLeft => mkPower(0), nPitchBendLeft => mkPitchBend(16#2000#), nNoteRight => mkNote(102), nPowerRight => mkPower(119), nPitchBendright => mkPitchBend(16#1000#), SS => timerocd_SPI_SS_n, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Writing Bank 3 Timer 27 = 00002000 | 66771000")); writeline(output, lineTemp); wait for 50 us; writeCommand(nCommand => "100001", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "0000") report "Expected OLD LED Status xxxx 0000" severity warning; wait for 50 us; readCommand(nCommand => "100000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "0001") report "Expected LED Status xxxx 0001" severity warning; wait for 50 us; writeCommand(nCommand => "100010", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "0001") report "Expected OLD LED Status xxxx 0001" severity warning; wait for 50 us; readCommand(nCommand => "100000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "0010") report "Expected LED Status xxxx 0010" severity warning; wait for 50 us; writeCommand(nCommand => "100100", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "0010") report "Expected OLD LED Status xxxx 0010" severity warning; wait for 50 us; readCommand(nCommand => "100000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "0100") report "Expected LED Status xxxx 0100" severity warning; wait for 50 us; writeCommand(nCommand => "110101", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "0000") report "Expected OLD LED Status 0000 xxxx" severity warning; wait for 50 us; readCommand(nCommand => "110000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "0101") report "Expected LED Status 0101 xxxx" severity warning; wait for 50 us; writeCommand(nCommand => "101000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "0100") report "Expected OLD LED Status xxxx 0100" severity warning; wait for 50 us; readCommand(nCommand => "100000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "1000") report "Expected LED Status xxxx 1000" severity warning; wait for 50 us; writeCommand(nCommand => "111010", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "0101") report "Expected OLD LED Status 0101 xxxx" severity warning; wait for 50 us; readCommand(nCommand => "110000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "1010") report "Expected LED Status 1010 xxxx" severity warning; wait for 50 us; writeCommand(nCommand => "100000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "1000") report "Expected OLD LED Status xxxx 1000" severity warning; wait for 50 us; readCommand(nCommand => "100000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "0000") report "Expected LED Status xxxx 0000" severity warning; wait for 50 us; writeCommand(nCommand => "110000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "1010") report "Expected OLD LED Status 1010 xxxx" severity warning; wait for 50 us; readCommand(nCommand => "110000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printLED(nLED => timerocd_LED); assert (nRcvCmdData = "0000") report "Expected LED Status 0000 xxxx" severity warning; wait for 50 us; readCommand(nCommand => "010000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printSW(nSW => nRcvCmdData(3 downto 0)); assert (nRcvCmdData = "1111") report "Expected Switch Status 1111" severity warning; wait for 50 us; timerocd_SW(3 downto 0) <= "0110"; readCommand(nCommand => "010000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printSW(nSW => nRcvCmdData(3 downto 0)); assert (nRcvCmdData = "0110") report "Expected Switch Status 0110" severity warning; wait for 50 us; timerocd_SW(3 downto 0) <= "1001"; readCommand(nCommand => "010000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printSW(nSW => nRcvCmdData(3 downto 0)); assert (nRcvCmdData = "1001") report "Expected Switch Status 1001" severity warning; wait for 50 us; timerocd_SW(3 downto 0) <= "1111"; readCommand(nCommand => "010000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); printSW(nSW => nRcvCmdData(3 downto 0)); assert (nRcvCmdData = "1111") report "Expected Switch Status 1111" severity warning; wait for 50 us; wait for 5 ms; report "Switching to Bank 0"; writeCommand(nCommand => "000100", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); assert (nRcvCmdData = "0011") report "Expected Current Data: 0011" severity warning; wait for 5 ms; writeTimerOC(nTimer => mkTimer(1), nNoteLeft => mkNote(108), nPowerLeft => mkPower(127), nPitchBendLeft => mkPitchBend(16#2000#), nNoteRight => mkNote(0), nPowerRight => mkPower(0), nPitchBendRight => mkPitchBend(16#2000#), SS => timerocd_SPI_SS_n, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Writing Bank 0 Timer 1 = 6C7F2000 | 00002000")); writeline(output, lineTemp); wait for 5 ms; writeTimerOC(nTimer => mkTimer(3), nNoteLeft => mkNote(0), nPowerLeft => mkPower(0), nPitchBendLeft => mkPitchBend(16#2000#), nNoteRight => mkNote(101), nPowerRight => mkPower(127), nPitchBendRight => mkPitchBend(16#2000#), SS => timerocd_SPI_SS_n, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Writing Bank 0 Timer 3 = 00002000 | 657F2000")); writeline(output, lineTemp); wait for 5 ms; readTimerOC(nTimer => mkTimer(3), nRetVal => nReceivedData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Read>> Bank 0 Timer 3 = ")); hwrite(lineTemp, nReceivedData); writeline(output, lineTemp); assert (nReceivedData = X"00002000_657F2000") report "Expected: 00002000 | 657F2000" severity warning; wait for 5 ms; readTimerOC(nTimer=>mkTimer(0), nRetVal => nReceivedData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Read>> Bank 0 Timer 0 = ")); hwrite(lineTemp, nReceivedData); writeline(output, lineTemp); assert (nReceivedData = X"15012000_00002000") report "Expected: 15012000 | 00002000" severity warning; wait for 5 ms; readTimerOC(nTimer => mkTimer(1), nRetVal => nReceivedData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Read>> Bank 0 Timer 1 = ")); hwrite(lineTemp, nReceivedData); writeline(output, lineTemp); assert (nReceivedData = X"6C7F2000_00002000") report "Expected: 6C7F2000 | 00002000" severity warning; wait for 5 ms; readTimerOC(nTimer=>mkTimer(0), nRetVal => nReceivedData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Read>> Bank 0 Timer 0 = ")); hwrite(lineTemp, nReceivedData); writeline(output, lineTemp); assert (nReceivedData = X"15012000_00002000") report "Expected: 15012000 | 00002000" severity warning; wait for 5 ms; readTimerOC(nTimer => mkTimer(1), nRetVal => nReceivedData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Read>> Bank 0 Timer 1 = ")); hwrite(lineTemp, nReceivedData); writeline(output, lineTemp); assert (nReceivedData = X"6C7F2000_00002000") report "Expected: 6C7F2000 | 00002000" severity warning; wait for 5 ms; readTimerOC(nTimer => mkTimer(3), nRetVal => nReceivedData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Read>> Bank 0 Timer 3 = ")); hwrite(lineTemp, nReceivedData); writeline(output, lineTemp); assert (nReceivedData = X"00002000_657F2000") report "Expected: 00002000 | 657F2000" severity warning; wait for 5 ms; readWriteTimerOC(nTimer => mkTimer(1), nNoteLeft => mkNote(56), nPowerLeft => mkPower(29), nPitchBendLeft => mkPitchBend(16#2000#), nNoteRight => mkNote(0), nPowerRight => mkPower(0), nPitchBendRight => mkPitchBend(16#2000#), nRetVal => nReceivedData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Read/Write>> Rewriting Bank 0 Timer 1 : OLD = ")); hwrite(lineTemp, nReceivedData); write(lineTemp, string'(" NEW = 381D2000 | 00002000")); writeline(output, lineTemp); assert (nReceivedData = X"6C7F2000_00002000") report "Expected: 6C7F2000 | 00002000" severity warning; wait for 5 ms; readTimerOC(nTimer=>mkTimer(0), nRetVal => nReceivedData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Read>> Bank 0 Timer 0 = ")); hwrite(lineTemp, nReceivedData); writeline(output, lineTemp); assert (nReceivedData = X"15012000_00002000") report "Expected: 15012000 | 00002000" severity warning; wait for 5 ms; readTimerOC(nTimer => mkTimer(1), nRetVal => nReceivedData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Read>> Bank 0 Timer 1 = ")); hwrite(lineTemp, nReceivedData); writeline(output, lineTemp); assert (nReceivedData = X"381D2000_00002000") report "Expected: 381D2000 | 00002000" severity warning; wait for 5 ms; writeTimerOC(nTimer => mkTimer(0), nNoteLeft => mkNote(0), nPowerLeft => mkPower(0), nPitchBendLeft => mkPitchBend(16#2000#), nNoteRight => mkNote(0), nPowerRight => mkPower(0), nPitchBendRight => mkPitchBend(16#2000#), SS => timerocd_SPI_SS_n, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Writing Bank 0 Timer 0 = 00002000 | 00002000")); writeline(output, lineTemp); wait for 5 ms; writeTimerOC(nTimer => mkTimer(3), nNoteLeft => mkNote(0), nPowerLeft => mkPower(0), nPitchBendLeft => mkPitchBend(16#2000#), nNoteRight => mkNote(0), nPowerRight => mkPower(0), nPitchBendRight => mkPitchBend(16#2000#), SS => timerocd_SPI_SS_n, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Writing Bank 0 Timer 3 = 00002000 | 00002000")); writeline(output, lineTemp); wait for 5 ms; writeTimerOC(nTimer => mkTimer(1), nNoteLeft => mkNote(0), nPowerLeft => mkPower(0), nPitchBendLeft => mkPitchBend(16#2000#), nNoteRight => mkNote(0), nPowerRight => mkPower(0), nPitchBendRight => mkPitchBend(16#2000#), SS => timerocd_SPI_SS_n, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Writing Bank 0 Timer 1 = 00002000 | 00002000")); writeline(output, lineTemp); wait for 5 ms; report "Testing Reset Logic"; writeTimerOC(nTimer => mkTimer(0), nNoteLeft => mkNote(21), nPowerLeft => mkPower(1), nPitchBendLeft => mkPitchBend(16#2000#), nNoteRight => mkNote(0), nPowerRight => mkPower(0), nPitchBendRight => mkPitchBend(16#2000#), SS => timerocd_SPI_SS_n, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Writing Bank 0 Timer 0 = 15012000 | 00002000")); writeline(output, lineTemp); wait for 10 ms; writeTimerOC(nTimer => mkTimer(1), nNoteLeft => mkNote(108), nPowerLeft => mkPower(127), nPitchBendLeft => mkPitchBend(16#2000#), nNoteRight => mkNote(0), nPowerRight => mkPower(0), nPitchBendRight => mkPitchBend(16#2000#), SS => timerocd_SPI_SS_n, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Writing Bank 0 Timer 1 = 6C7F2000 | 00002000")); writeline(output, lineTemp); wait for 5 ms; writeTimerOC(nTimer => mkTimer(3), nNoteLeft => mkNote(0), nPowerLeft => mkPower(0), nPitchBendLeft => mkPitchBend(16#2000#), nNoteRight => mkNote(101), nPowerRight => mkPower(127), nPitchBendRight => mkPitchBend(16#2000#), SS => timerocd_SPI_SS_n, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Writing Bank 0 Timer 3 = 00002000 | 657F2000")); writeline(output, lineTemp); wait for 10 ms; report "Sending Reset"; writeCommand(nCommand => "000000", nCmdData => nRcvCmdData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); wait for 5 ms; readTimerOC(nTimer => mkTimer(0), nRetVal => nReceivedData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Read>> Bank 0 Timer 0 = ")); hwrite(lineTemp, nReceivedData); writeline(output, lineTemp); assert (nReceivedData = X"00002000_00002000") report "Expected: 00002000 | 00002000" severity warning; wait for 5 ms; readTimerOC(nTimer=>mkTimer(1), nRetVal => nReceivedData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Read>> Bank 0 Timer 1 = ")); hwrite(lineTemp, nReceivedData); writeline(output, lineTemp); assert (nReceivedData = X"00002000_00002000") report "Expected: 00002000 | 00002000" severity warning; wait for 5 ms; readTimerOC(nTimer => mkTimer(3), nRetVal => nReceivedData, SS => timerocd_SPI_SS_n, MISO => timerocd_SPI_MISO, MOSI => timerocd_SPI_MOSI, CLK => timerocd_SPI_CLK); write(lineTemp, string'("Read>> Bank 0 Timer 3 = ")); hwrite(lineTemp, nReceivedData); writeline(output, lineTemp); assert (nReceivedData = X"00002000_00002000") report "Expected: 00002000 | 00002000" severity warning; wait for 5 ms; -- Add more tests here wait; end process stimproc; end behavior;