Subversion Repositories tinyvliw8

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
library altera;
use altera.altera_syn_attributes.all;
 
entity alteraDK1 is
	port (
		clock	: in 	std_logic;
 
		-- 7-Segments-LEDs
		hex0	: out	std_logic_vector(6 downto 0);
		hex1	: out	std_logic_vector(6 downto 0);
		hex2	: out	std_logic_vector(6 downto 0);
		hex3	: out	std_logic_vector(6 downto 0);
 
		-- GPIO
		jp1 	: inout	std_logic_vector(0 to 35);
		jp2 	: inout	std_logic_vector(0 to 35);
 
		-- UART
		uart0_rxd : in std_logic;
		uart0_txd : out std_logic;
 
		-- keys
		key       : in  std_logic_vector(3 downto 0);
		-- switches
		sw        : in  std_logic_vector(9 downto 0);		
 
		-- LEDs
		led_red   : out std_logic_vector(9 downto 0);
		led_green : out std_logic_vector(7 downto 0)
	);
end alteraDK1;
 
architecture rtl of AlteraDK1 is
 
component instMem IS
	PORT (
		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
		data			: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		inclock		: IN STD_LOGIC  := '1';
		outclock		: IN STD_LOGIC ;
		wren			: IN STD_LOGIC ;
		q				: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
END component;
 
component dataMem IS
	PORT (
		address	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		inclock	: IN STD_LOGIC  := '1';
		outclock	: IN STD_LOGIC ;
		wren		: IN STD_LOGIC ;
		q			: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END component;
 
component vliwProc
	port (
		clk           : in  std_logic;
 
		instMemAddr   : out std_logic_vector(10 downto 0);
		instMemDataIn : in  std_logic_vector(31 downto 0);
		instMemEn_n   : out std_logic;
 
		ioMemAddr    : out std_logic_vector(7 downto 0);
		ioMemDataOut : out std_logic_vector(7 downto 0);
		ioMemDataIn  : in  std_logic_vector(7 downto 0);
		ioMemWr_n    : out std_logic;
		ioMemEn_n    : out std_logic;
 
		-- IO bus
		dataMemAddr    : out std_logic_vector(7 downto 0);
		dataMemDataOut : out std_logic_vector(7 downto 0);
		dataMemDataIn  : in  std_logic_vector(7 downto 0);
		dataMemWr_n    : out std_logic;
		dataMemEn_n    : out std_logic;
 
		irqLine        : in  std_logic_vector(4 downto 0);
		irqLineAck     : out std_logic_vector(4 downto 0);
 
		stall_n      : in std_logic;
		stalled_n    : out std_logic;
 
		rst_n        : in std_logic
	);
end component;
 
component spiSlave
	PORT (
		sclk      : IN  STD_LOGIC;
		cs        : IN  STD_LOGIC;
		mosi      : IN  STD_LOGIC;
		miso      : OUT STD_LOGIC;
		addr      : OUT std_logic_vector(10 downto 0);
		memSel    : out std_logic_vector(1 downto 0);
		writeEn_n : OUT STD_LOGIC;
		readEn_n  : OUT STD_LOGIC;
 
		dataOut	 : OUT std_logic_vector(31 downto 0);
		dataIn    : IN std_logic_vector(31 downto 0);
 
		rst_n     : IN  STD_LOGIC
	);
end component;
 
component ioport
	port (
    		cs_n     : IN  STD_LOGIC; 			            -- chip select signal
 
			clk      : IN  STD_LOGIC;
 
			-- memory interface
    		mdbwr_n  : IN  STD_LOGIC;                    -- write enable signal    
   		mdb_i   	: IN  STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from data bus
    		mdb_o   	: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to data bus    
    		mab   	: IN  STD_LOGIC_VECTOR(2 downto 0);	-- address registers 
 
			-- interrupt interface
			irq      : out std_logic;
			irqAck   : in std_logic;
 
    		-- port interface
    		PnIN  	: IN  STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from pad (gpio in)
    		PnOUT   	: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to pad (gpio out)
    		PnOEN  	: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- port direction (low active)
 
    		-- MODxIN   : IN  STD_LOGIC_VECTOR(7 DOWNTO 0); 	-- data to peripheral
    		-- MODxDIR  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0); 	-- direction
    		-- MODxOUT  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);   	-- data from peripheral 
 
   		rst_n		: IN STD_LOGIC			
  		);
end component;
 
component timer
	PORT (
		clk       : in std_logic;
 
		addr      : in std_logic_vector(2 downto 0);	   -- register address
 
		writeEn_n : in  STD_LOGIC;	                     -- write enable, low active
		readEn_n  : in  STD_LOGIC;                      -- read enable, low active
 
		dataOut   : OUT std_logic_vector(7 downto 0);	-- data bus for writing register
		dataIn    : IN std_logic_vector(7 downto 0);    -- data bus for reading register
 
		irq       : out std_logic;
		irq_ack   : in  std_logic;
 
		rst_n     : IN  STD_LOGIC                        -- asynchr. reset, low active
	);
end component;
 
component gendelay
	generic (n: integer := 1);
	port (
		a_in	: in	std_logic;
		a_out	: out	std_logic
	);
end component;
 
	signal mclk_s   : std_logic;                          -- main clock
 
	-- mdu interface
	signal mduClk_s     : std_logic;
	signal mduDataOut_s : std_logic_vector(31 downto 0);
	signal mduEn_n_s : std_logic;
	signal mduIoDataOut_s : std_logic_vector(7 downto 0);	
 
	-- instruction memory interface
	signal instMemAddr_s   : std_logic_vector(10 downto 0);
	signal instMemDataIn_s : std_logic_vector(31 downto 0);
	signal instMemInClk_s  : std_logic;
	signal instMemOutClk_s : std_logic;
	signal instMemWrEn_s   : std_logic;
 
	signal instRdEn_n_s    : std_logic;
	signal instRdEnDly_n_s : std_logic;
	signal instWrEn_n_s    : std_logic;
 
	signal instAddr_s    : std_logic_vector(10 downto 0);
	signal instDataOut_s : std_logic_vector(31 downto 0);
	signal instEn_n_s    : std_logic;
 
	-- IO bus
	signal ioAddr_s    : std_logic_vector(7 downto 0);
	signal ioDataOut_s : std_logic_vector(7 downto 0);
	signal ioDataIn_s  : std_logic_vector(7 downto 0);
	signal ioEn_n_s    : std_logic;
	signal ioWr_n_s    : std_logic;
 
	-- GPIO signals
	signal ioDataGpio_s : std_logic_vector(7 downto 0);	
	signal ioPortEn_n_s : std_logic;
	signal ioPortIrq_s  : std_logic;
 
	-- Data bus
	signal procDataAddr_s : std_logic_vector(7 downto 0);
	signal procDataOut_s  : std_logic_vector(7 downto 0);
	signal procDataIn_s   : std_logic_vector(7 downto 0);
	signal procDataWr_n_s : std_logic;
	signal procDataEn_n_s : std_logic;
 
	signal dataMemAddr_s   : std_logic_vector(7 downto 0);
	signal dataMemIn_s     : std_logic_vector(7 downto 0);
	signal dataWrEn_s      : std_logic;
	signal dataRdEnDly_n_s : std_logic;
	signal dataMemInClk_s  : std_logic;
	signal dataMemOutClk_s : std_logic;
	signal dataRdEn_n_s    : std_logic;
	signal dataWrEn_n_s    : std_logic;
 
	signal rst_n_s     : std_logic;
 
	signal stall_n_s   : std_logic;
	signal stalled_n_s : std_logic;
 
	signal irqLine_s      : std_logic_vector(4 downto 0);
	signal irqLineAck_s   : std_logic_vector(4 downto 0);
 
	-- timer signals 
	signal timer_irq_s      : std_logic;
	signal ioTimerEn_n_s    : std_logic;
	signal ioTimerDataOut_s : std_logic_vector(7 downto 0);
 
	-- spi slave
	signal spiCsIn_s    : std_logic;	
	signal sclk_s       : std_logic;
	signal cs_s         : std_logic;
	signal mosi_s       : std_logic;
	signal miso_s       : std_logic;
	signal spiAddr_s    : std_logic_vector(10 downto 0);
	signal spiMemSel_s  : std_logic_vector(1 downto 0);
	signal spiWrEn_n_s  : std_logic;
	signal spiRdEn_n_s  : std_logic;
	signal spiDataOut_s : std_logic_vector(31 downto 0);
	signal spiDataIn_s  : std_logic_vector(31 downto 0);
 
	signal gpio_in_s  : std_logic_vector(7 downto 0);
	signal gpio_out_s : std_logic_vector(7 downto 0);
	signal gpio_dir_s : std_logic_vector(7 downto 0);
 
begin
 
	gpio_gen: for i in 7 downto 0 generate
	begin
		jp2(i) <= gpio_out_s(i) when gpio_dir_s(i) = '1' else
		          'Z';
		gpio_in_s(i) <= jp2(i);
	end generate;
 
	rst_sync: process (clock)
	begin
		if clock'event and clock = '1' then
			rst_n_s <= key(0);
		end if;
	end process;
 
	mclk_s <= clock;
 
	irqLine_s <= ioPortIrq_s & timer_irq_s & "000";
 
 
	-- instruction memory
	---------------------
 
	instMemOut_delay_i: gendelay
		generic map (n => 2)
		port map (
			a_in	=> instRdEn_n_s,
			a_out	=> instRdEnDly_n_s
		);
 
	instMem_i : instMem
	port map (
		address  => instMemAddr_s,
		data     => instMemDataIn_s,
		inclock  => instMemInClk_s,
		outclock => instMemOutClk_s,
		wren     => instMemWrEn_s,
		q        => instDataOut_s
	);
 
	instMemAddr_s <= spiAddr_s when cs_s = '0' and spiMemSel_s = "00" else
	                 instAddr_s;
 
	instMemDataIn_s <= spiDataOut_s;
	instMemWrEn_s   <= not(instWrEn_n_s);
 
	instMemInClk_s  <= not(instRdEn_n_s) and not(instRdEnDly_n_s xor instWrEn_n_s);
	instMemOutClk_s <= not(instMemInClk_s);
 
	instRdEn_n_s <= '0' when (cs_s = '0' and spiRdEn_n_s = '0' and spiMemSel_s = "00") or
	                         (cs_s = '1' and instEn_n_s = '0') else
					    '1';
	instWrEn_n_s <= '0' when (cs_s = '0' and spiWrEn_n_s = '0' and spiMemSel_s = "00") else
	                '1';
 
	-- data memory
	--------------------------
	dataMem_i : dataMem
	port map (
		address  => dataMemAddr_s,
		data     => dataMemIn_s,
		inclock  => dataMemInClk_s,
		outclock => dataMemOutClk_s,
		wren     => dataWrEn_s,
		q        => procDataOut_s
	);
 
	dataMemAddr_s <= spiAddr_s(7 downto 0) when cs_s = '0' and spiMemSel_s = "01" else
	                 procDataAddr_s;
 
	dataMemIn_s   <= spiDataOut_s(7 downto 0) when cs_s = '0' and spiMemSel_s = "01" else
	                 procDataIn_s;
	dataWrEn_s    <= not(dataWrEn_n_s);
 
	dataMemOutClk_delay_i: gendelay
		generic map (n => 2)
		port map (
			a_in	=> dataRdEn_n_s,
			a_out	=> dataRdEnDly_n_s
		);
 
	dataMemInClk_s  <= not(dataRdEn_n_s) and not(dataRdEnDly_n_s xor dataWrEn_n_s);
	dataMemOutClk_s <= not(dataMemInClk_s);
 
 
	dataRdEn_n_s <= '0' when (cs_s = '0' and spiRdEn_n_s = '0' and spiMemSel_s = "01") or
	                         (cs_s = '1' and procDataEn_n_s = '0') else
					    '1';
	dataWrEn_n_s <= '0' when (cs_s = '0' and spiWrEn_n_s = '0' and spiMemSel_s = "01") or
	                         (cs_s = '1' and procDataWr_n_s = '0') else
	                '1';
 
	ioDataIn_s <= ioDataGpio_s     when ioPortEn_n_s = '0' else
	              ioTimerDataOut_s when ioTimerEn_n_s = '0' else
					  mduIoDataOut_s     when mduEn_n_s = '0' else
	              (others => '0');
 
	vliwProc_i : vliwProc
	port map (
		clk            => mclk_s,
 
		instMemAddr    => instAddr_s,
		instMemDataIn  => instDataOut_s,
		instMemEn_n    => instEn_n_s,
 
		ioMemAddr      => ioAddr_s,
		ioMemDataOut   => ioDataOut_s,
		ioMemDataIn    => ioDataIn_s,
		ioMemEn_n      => ioEn_n_s,
		ioMemWr_n      => ioWr_n_s,
 
		dataMemAddr    => procDataAddr_s,
		dataMemDataOut => procDataIn_s,
		dataMemDataIn  => procDataOut_s,
		dataMemEn_n    => procDataEn_n_s,
		dataMemWr_n    => procDataWr_n_s,
 
		irqLine        => irqLine_s,
		irqLineAck     => irqLineAck_s,
 
		stall_n        => stall_n_s,
		stalled_n      => stalled_n_s,
 
		rst_n          => rst_n_s
	);
 
	-- instruction  memory (read only)
	----------------------------------
	spiSlave_i: spiSlave
	port map (
		sclk      => sclk_s,
		cs        => cs_s,
		mosi      => mosi_s,
		miso      => miso_s,
 
		addr      => spiAddr_s,
		memSel    => spiMemSel_s,
 
		dataOut   => spiDataOut_s,
		dataIn    => spiDataIn_s,
 
		writeEn_n => spiWrEn_n_s,
		readEn_n  => spiRdEn_n_s,
 
		-- rst_n     => '0'
		rst_n     => rst_n_s
	);
 
	spiCsIn_s <= jp2(32);
	stall_n_s <= '0' when spiCsIn_s = '0' else
	             '1';
	cs_s <= '0' when  spiCsIn_s = '0' and stalled_n_s = '0' else
	        '1';
	jp2(32) <= 'Z';
 
	spiDataIn_s <= instDataOut_s(31 downto 0) when cs_s = '0' and spiMemSel_s = "00" else
	               x"000000" & procDataOut_s  when cs_s = '0' and spiMemSel_s = "01" else
	               (others => '0');
	jp2(33) <= '1'    when spiCsIn_s = '0' and stalled_n_s = '1' else
	           miso_s when cs_s = '0' else
	           'Z';
	mosi_s <= jp2(34);
	sclk_s <= jp2(35);
 
	ioPortEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00010" else
	                '1';
 
	ioport_i : ioport
	port map (
  		cs_n     => ioPortEn_n_s,
		clk      => sclk_s,
 
  		mdbwr_n  => ioWr_n_s,
 		mdb_i   	=> ioDataOut_s,
  		mdb_o   	=> ioDataGpio_s,  
  		mab   	=> ioAddr_s(2 downto 0),
 
		irq      => ioPortIrq_s,
		irqAck   => irqLineAck_s(4),
 
  		-- port interface
  		PnIN  	=> gpio_in_s,
  		PnOUT   	=> gpio_out_s,
  		PnOEN  	=> gpio_dir_s,
 
 		rst_n		=> rst_n_s
	);
 
	ioTimerEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00011" else
	                 '1';
 
	timer_i : timer
	port map (
		clk       => mclk_s,
		-- clk       => '0',
 
		addr      => ioAddr_s(2 downto 0),
 
		writeEn_n => ioWr_n_s,
		readEn_n  => ioTimerEn_n_s,
 
		dataOut   => ioTimerDataOut_s,
		dataIn    => ioDataOut_s,
 
		irq       => timer_irq_s,
		irq_ack   => irqLineAck_s(3),
 
		rst_n     => rst_n_s
	);
 
end rtl;