Subversion Repositories tinyvliw8

-----------------------------------------------------------------
-- Project: Aeternitas
-- Author:  Oliver Stecklina <stecklina@ihp-microelectronics.com
-- Date:    11.11.2013 
-- File:    statusReg.vhd
-- Design:  AeternitasSWUR
-----------------------------------------------------------------
-- Description : Status register.
-----------------------------------------------------------------
-- $Log$
-----------------------------------------------------------------
 
library ieee;
 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity vliwProc_statusReg is
	port (
		state      : in std_logic_vector(3 downto 0);
 
		iretEn_n   : in std_logic;
		ioEn_n     : in std_logic;
		irqEn      : in std_logic;
		flagsEn_n  : in std_logic;
 
		flagsIn    : in std_logic_vector(1 downto 0);       -- carry | zero
 
		dataIn     : in  std_logic_vector(7 downto 0);
		dataOut    : out std_logic_vector(7 downto 0);
 
		rst_n      : in std_logic
	);
end vliwProc_statusReg;
 
architecture behavior of vliwProc_statusReg is
 
	signal rst_n_s      : std_logic;
 
	-- signal statusReg_s  : std_logic_vector(2 downto 0);
 
	signal stallEn_s    : std_logic;
	signal stallEvt_s   : std_logic;
 
	signal irqEn_s      : std_logic;
	signal irqEvt_s     : std_logic;
	signal ieEn_s       : std_logic;
 
	signal flags_s      : std_logic_vector(1 downto 0);
	signal flagsIInt_s  : std_logic_vector(1 downto 0);
 
	signal state2_s     : std_logic;
 
begin
 
	rst_n_s <= rst_n;
 
	state2_s <= state(2);
 
   -----------------------------------------------------------------------------
	--
	-- setting in-interrupt flag, switches to 
	--      '1', when an irq ack occures - falling edge on irqEn_n
	--      '0', when pc is loaded by load/store unit - falling edge on iretEn_n
	--
   -----------------------------------------------------------------------------
	irqEn_proc : process(rst_n_s, irqEvt_s)
	begin
		if (rst_n_s = '0') then
			irqEn_s <= '0';
		else
			if (irqEvt_s'event and irqEvt_s = '1') then
				if (irqEn = '1') then
					irqEn_s <= '1';
				elsif (iretEn_n = '0') then
					irqEn_s <= '0';
				end if;
			end if;
		end if;
	end process;
 
	irqEvt_s <= irqEn xor not(iretEn_n);
 
   -----------------------------------------------------------------------------
	--
	-- setting processor stall, switches to 
	--      '1', when a '1' is loaded via dataIn(7) - falling edge on ioEn_n
	--      '0', when an interrupt occures - falling edge on irqEn_n
	--
   -----------------------------------------------------------------------------
	stallEn_proc : process(rst_n_s, stallEvt_s)
	begin
		if (rst_n_s = '0') then
			stallEn_s <= '0';
		else
			if (stallEvt_s'event and stallEvt_s = '1') then
				if (irqEn = '1') then
					stallEn_s <= '0';
				elsif (ioEn_n = '0') then
					stallEn_s <= dataIn(7);
				end if;
			end if;
		end if;
	end process;
 
	stallEvt_s <= (not(ioEn_n) and not(state2_s)) xor irqEn;
 
	ieEn_proc : process(rst_n_s, ioEn_n)
	begin
		if (rst_n_s = '0') then
			ieEn_s <= '0';
		else
			if (ioEn_n'event and ioEn_n = '0') then
				ieEn_s <= dataIn(3);
			end if;
		end if;
	end process;
 
	flagsEn_proc : process(rst_n_s, state(3))
	begin
		if (rst_n_s = '0') then
			flags_s     <= (others => '0');
			flagsIInt_s <= (others => '0');
		else
			if (state(3)'event and state(3) = '1') then
				if (irqEn_s = '0') then
					if (flagsEn_n = '0') then
						flags_s <= flagsIn;
					else
						flags_s <= (others => '0');
					end if;
				else
					if (flagsEn_n = '0') then
						flagsIInt_s <= flagsIn;
					else
						flagsIInt_s <= (others => '0');
					end if;
				end if;
			end if;
		end if;
	end process;
 
   -----------------------------------------------------------------------------
	--
	-- Status register
	--   stall | 0 | carry | zero | ie | 0 | 0 | iint
	--
   -----------------------------------------------------------------------------
 
	dataOut <= stallEn_s & "0" & flags_s & ieEn_s & "00" & '0'     when rst_n_s = '1' and irqEn_s = '0' else
	           stallEn_s & "0" & flagsIInt_s & ieEn_s & "00" & '1' when rst_n_s = '1' and irqEn_s = '1' else
				  (others => '0');
 
end behavior;