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https://opencores.org/ocsvn/usb_fpga_1_2/usb_fpga_1_2/trunk
Subversion Repositories usb_fpga_1_2
[/] [usb_fpga_1_2/] [trunk/] [examples/] [usb-fpga-1.11/] [1.11a/] [memtest/] [fpga/] [ipcore_dir/] [mem0.xco] - Rev 8
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SET designentry = VHDL
SET BusFormat = BusFormatAngleBracketNotRipped
SET devicefamily = spartan6
SET device = xc6slx9
SET package = ftg256
SET speedgrade = -3
SET FlowVendor = Foundation_ISE
SET VerilogSim = True
SET VHDLSim = True
SELECT MIG family Xilinx,_Inc. 3.5
CSET component_name=mem0
CSET xml_input_file=./mem0/user_design/mig.prj