URL
https://opencores.org/ocsvn/usb_fpga_1_2/usb_fpga_1_2/trunk
Subversion Repositories usb_fpga_1_2
[/] [usb_fpga_1_2/] [trunk/] [examples/] [usb-fpga-1.15/] [1.15a/] [memtest/] [fpga/] [ipcore_dir/] [mem0/] [user_design/] [mig.prj] - Rev 9
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<?xml version="1.0" encoding="UTF-8"?>
<Project NoOfControllers="1" >
<ModuleName>mem0</ModuleName>
<TargetFPGA>xc6slx45-csg484/-2</TargetFPGA>
<Version>3.5</Version>
<Controller number="3" >
<MemoryDevice>DDR2_SDRAM/Components/MT47H64M16XX-25E</MemoryDevice>
<TimePeriod>2500</TimePeriod>
<EnableVoltageRange>1</EnableVoltageRange>
<DataMask>1</DataMask>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>13</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<TimingParameters>
<Parameters twtr="7.5" trefi="7.8" twr="15" trtp="7.5" trfc="127.5" trp="12.5" tras="40" trcd="12.5" />
</TimingParameters>
<mrBurstLength name="Burst Length" >4(010)</mrBurstLength>
<mrCasLatency name="CAS Latency" >5</mrCasLatency>
<emrDllEnable name="DLL Enable" >Enable-Normal</emrDllEnable>
<emrOutputDriveStrength name="Output Drive Strength" >Fullstrength</emrOutputDriveStrength>
<emrRTT name="RTT (nominal) - ODT" >RTT Disabled</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="OCD Operation" >OCD Exit</emrOCD>
<emrDQS name="DQS# Enable" >Enable</emrDQS>
<emrRDQS name="RDQS Enable" >Disable</emrRDQS>
<emrOutputs name="Outputs" >Enable</emrOutputs>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Disable</mr2SelfRefreshTempRange>
<Class>Class II</Class>
<DataClass>Class II</DataClass>
<InputPinTermination>CALIB_TERM</InputPinTermination>
<DataTermination>25 Ohms</DataTermination>
<CalibrationRowAddress></CalibrationRowAddress>
<CalibrationColumnAddress></CalibrationColumnAddress>
<CalibrationBankAddress></CalibrationBankAddress>
<BypassCalibration>1</BypassCalibration>
<DebugSignals>Disable</DebugSignals>
<SystemClock>Single-Ended</SystemClock>
<Configuration>Two 32-bit bi-directional and four 32-bit unidirectional ports</Configuration>
<RzqPin>AA2</RzqPin>
<ZioPin>Y2</ZioPin>
<PortsSelected>Port0,Port1,Port2,Port3,Port4,Port5</PortsSelected>
<PortDirections>Bi-directional,Bi-directional,Write,Read,Write,Read</PortDirections>
<UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
<ArbitrationAlgorithm>Round Robin</ArbitrationAlgorithm>
<TimeSlot0>012345</TimeSlot0>
<TimeSlot1>123450</TimeSlot1>
<TimeSlot2>234501</TimeSlot2>
<TimeSlot3>345012</TimeSlot3>
<TimeSlot4>450123</TimeSlot4>
<TimeSlot5>501234</TimeSlot5>
<TimeSlot6>012345</TimeSlot6>
<TimeSlot7>123450</TimeSlot7>
<TimeSlot8>234501</TimeSlot8>
<TimeSlot9>345012</TimeSlot9>
<TimeSlot10>450123</TimeSlot10>
<TimeSlot11>501234</TimeSlot11>
</Controller>
</Project>