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https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk
Subversion Repositories usbhostslave
[/] [usbhostslave/] [trunk/] [usbDevice/] [RTL/] [usbHostSlaveReg_define.v] - Rev 43
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// ------------------------------ usbHostSlaveReg_define.v ---------------------------- `include "wishBoneBus_h.v" `include "usbHostSlave_h.v" `define RA_EP0_CONTROL_REG `SCREG_BASE+`ENDPOINT_CONTROL_REG `define RA_EP0_STATUS_REG `SCREG_BASE+`ENDPOINT_STATUS_REG `define RA_EP0_TRANSTYPE_STATUS_REG `SCREG_BASE+`ENDPOINT_TRANSTYPE_STATUS_REG `define RA_EP0_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+`NAK_TRANSTYPE_STATUS_REG `define RA_EP1_CONTROL_REG `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_CONTROL_REG `define RA_EP1_STATUS_REG `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_STATUS_REG `define RA_EP1_TRANSTYPE_STATUS_REG `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_TRANSTYPE_STATUS_REG `define RA_EP1_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`NAK_TRANSTYPE_STATUS_REG `define RA_EP2_CONTROL_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`ENDPOINT_CONTROL_REG `define RA_EP2_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`ENDPOINT_STATUS_REG `define RA_EP2_TRANSTYPE_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)`+`ENDPOINT_TRANSTYPE_STATUS_REG `define RA_EP2_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`NAK_TRANSTYPE_STATUS_REG `define RA_EP3_CONTROL_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_CONTROL_REG `define RA_EP3_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_STATUS_REG `define RA_EP3_TRANSTYPE_STATUS_REG `SCREG_BASE+(NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_TRANSTYPE_STATUS_REG `define RA_EP3_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`NAK_TRANSTYPE_STATUS_REG `define RA_SC_CONTROL_REG `SCREG_BASE+`SC_CONTROL_REG `define RA_SC_LINE_STATUS_REG `SCREG_BASE+`SC_LINE_STATUS_REG `define RA_SC_INTERRUPT_STATUS_REG `SCREG_BASE+`SC_INTERRUPT_STATUS_REG `define RA_SC_INTERRUPT_MASK_REG `SCREG_BASE+`SC_INTERRUPT_MASK_REG `define RA_SC_ADDRESS `SCREG_BASE+`SC_ADDRESS `define RA_SC_FRAME_NUM_MSP `SCREG_BASE+`SC_FRAME_NUM_MSP `define RA_SC_FRAME_NUM_LSP `SCREG_BASE+`SC_FRAME_NUM_LSP `define RA_EP0_RX_FIFO_DATA_REG `EP0_RX_FIFO_BASE+`FIFO_DATA_REG `define RA_EP0_RX_FIFO_STATUS_REG `EP0_RX_FIFO_BASE+`FIFO_STATUS_REG `define RA_EP0_RX_FIFO_DATA_COUNT_MSB `EP0_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB `define RA_EP0_RX_FIFO_DATA_COUNT_LSB `EP0_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB `define RA_EP0_RX_FIFO_CONTROL_REG `EP0_RX_FIFO_BASE+`FIFO_CONTROL_REG `define RA_EP0_TX_FIFO_DATA_REG `EP0_TX_FIFO_BASE+`FIFO_DATA_REG `define RA_EP0_TX_FIFO_STATUS_REG `EP0_TX_FIFO_BASE+`FIFO_STATUS_REG `define RA_EP0_TX_FIFO_DATA_COUNT_MSB `EP0_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB `define RA_EP0_TX_FIFO_DATA_COUNT_LSB `EP0_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB `define RA_EP0_TX_FIFO_CONTROL_REG `EP0_TX_FIFO_BASE+`FIFO_CONTROL_REG `define RA_EP1_RX_FIFO_DATA_REG `EP1_RX_FIFO_BASE+`FIFO_DATA_REG `define RA_EP1_RX_FIFO_STATUS_REG `EP1_RX_FIFO_BASE+`FIFO_STATUS_REG `define RA_EP1_RX_FIFO_DATA_COUNT_MSB `EP1_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB `define RA_EP1_RX_FIFO_DATA_COUNT_LSB `EP1_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB `define RA_EP1_RX_FIFO_CONTROL_REG `EP1_RX_FIFO_BASE+`FIFO_CONTROL_REG `define RA_EP1_TX_FIFO_DATA_REG `EP1_TX_FIFO_BASE+`FIFO_DATA_REG `define RA_EP1_TX_FIFO_STATUS_REG `EP1_TX_FIFO_BASE+`FIFO_STATUS_REG `define RA_EP1_TX_FIFO_DATA_COUNT_MSB `EP1_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB `define RA_EP1_TX_FIFO_DATA_COUNT_LSB `EP1_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB `define RA_EP1_TX_FIFO_CONTROL_REG `EP1_TX_FIFO_BASE+`FIFO_CONTROL_REG `define RA_EP2_RX_FIFO_DATA_REG `EP2_RX_FIFO_BASE+`FIFO_DATA_REG `define RA_EP2_RX_FIFO_STATUS_REG `EP2_RX_FIFO_BASE+`FIFO_STATUS_REG `define RA_EP2_RX_FIFO_DATA_COUNT_MSB `EP2_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB `define RA_EP2_RX_FIFO_DATA_COUNT_LSB `EP2_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB `define RA_EP2_RX_FIFO_CONTROL_REG `EP2_RX_FIFO_BASE+`FIFO_CONTROL_REG `define RA_EP2_TX_FIFO_DATA_REG `EP2_TX_FIFO_BASE+`FIFO_DATA_REG `define RA_EP2_TX_FIFO_STATUS_REG `EP2_TX_FIFO_BASE+`FIFO_STATUS_REG `define RA_EP2_TX_FIFO_DATA_COUNT_MSB `EP2_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB `define RA_EP2_TX_FIFO_DATA_COUNT_LSB `EP2_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB `define RA_EP2_TX_FIFO_CONTROL_REG `EP2_TX_FIFO_BASE+`FIFO_CONTROL_REG `define RA_EP3_RX_FIFO_DATA_REG `EP3_RX_FIFO_BASE+`FIFO_DATA_REG `define RA_EP3_RX_FIFO_STATUS_REG `EP3_RX_FIFO_BASE+`FIFO_STATUS_REG `define RA_EP3_RX_FIFO_DATA_COUNT_MSB `EP3_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB `define RA_EP3_RX_FIFO_DATA_COUNT_LSB `EP3_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB `define RA_EP3_RX_FIFO_CONTROL_REG `EP3_RX_FIFO_BASE+`FIFO_CONTROL_REG `define RA_EP3_TX_FIFO_DATA_REG `EP3_TX_FIFO_BASE+`FIFO_DATA_REG `define RA_EP3_TX_FIFO_STATUS_REG `EP3_TX_FIFO_BASE+`FIFO_STATUS_REG `define RA_EP3_TX_FIFO_DATA_COUNT_MSB `EP3_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB `define RA_EP3_TX_FIFO_DATA_COUNT_LSB `EP3_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB `define RA_EP3_TX_FIFO_CONTROL_REG `EP3_TX_FIFO_BASE+`FIFO_CONTROL_REG `define RA_HOST_SLAVE_MODE `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG `define RA_HOST_SLAVE_VERSION `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG
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