URL
https://opencores.org/ocsvn/z80soc/z80soc/trunk
Subversion Repositories z80soc
[/] [z80soc/] [trunk/] [V0.7.1a/] [S3E/] [memoryCores/] [rom.xise] - Rev 42
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These should not be modified.--><!-- --><property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_DesignName" xil_pn:value="rom" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/><property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/><property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-11-23T01:48:43" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="4AE013FF32DB40AE9F3E2950A341381C" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/></properties><bindings/><libraries/><autoManagedFiles><!-- The following files are identified by `include statements in verilog --><!-- source files and are automatically managed by Project Navigator. --><!-- --><!-- Do not hand-edit this section, as it will be overwritten when the --><!-- project is analyzed based on files automatically identified as --><!-- include files. --></autoManagedFiles></project>