Subversion Repositories 1g_ethernet_dpi

//---------------------------------------------------------------------------
// File       : tri_mode_ethernet_mac_0_support_resets.v
// Author     : Xilinx Inc.
// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
// Description: This module holds the shared resets for the IDELAYCTRL
//              and the MMCM
//------------------------------------------------------------------------------
 
`timescale 1ns / 1ps
 
module tri_mode_ethernet_mac_0_support_resets
(
    input           glbl_rstn,
    input           refclk,
    input           idelayctrl_ready,
    output          idelayctrl_reset_out,
    input           gtx_clk,
    input           gtx_dcm_locked,
    output          gtx_mmcm_rst_out           // The reset pulse for the MMCM.
);
 
   wire             glbl_rst;
 
   wire             idelayctrl_reset_in;       // Used to trigger reset_sync generation in refclk domain.
   wire             idelayctrl_reset_sync;     // Used to create a reset pulse in the IDELAYCTRL refclk domain.
   reg   [3:0]      idelay_reset_cnt;          // Counter to create a long IDELAYCTRL reset pulse.
   reg              idelayctrl_reset;
 
   wire             gtx_mmcm_rst_in;
   wire             gtx_dcm_locked_int;
   wire             gtx_dcm_locked_sync;
   reg              gtx_dcm_locked_reg = 1;
   reg              gtx_dcm_locked_edge = 1;
 
 
 assign glbl_rst              = !glbl_rstn;
 
 //----------------------------------------------------------------------------
 // Reset circuitry associated with the IDELAYCTRL
 //----------------------------------------------------------------------------
 
 assign idelayctrl_reset_out  = idelayctrl_reset;
 assign idelayctrl_reset_in   = glbl_rst || !idelayctrl_ready;
 
   // Create a synchronous reset in the IDELAYCTRL refclk clock domain.
   tri_mode_ethernet_mac_0_reset_sync idelayctrl_reset_gen (
      .clk              (refclk),
      .enable           (1'b1),
      .reset_in         (idelayctrl_reset_in),
      .reset_out        (idelayctrl_reset_sync)
   );
 
   // Reset circuitry for the IDELAYCTRL reset.
 
   // The IDELAYCTRL must experience a pulse which is at least 50 ns in
   // duration.  This is ten clock cycles of the 200MHz refclk.  Here we
   // drive the reset pulse for 12 clock cycles.
   always @(posedge refclk)
   begin
      if (idelayctrl_reset_sync) begin
         idelay_reset_cnt     <= 4'b0000;
         idelayctrl_reset     <= 1'b1;
      end
      else begin
         case (idelay_reset_cnt)
            4'b0000 : idelay_reset_cnt <= 4'b0001;
            4'b0001 : idelay_reset_cnt <= 4'b0010;
            4'b0010 : idelay_reset_cnt <= 4'b0011;
            4'b0011 : idelay_reset_cnt <= 4'b0100;
            4'b0100 : idelay_reset_cnt <= 4'b0101;
            4'b0101 : idelay_reset_cnt <= 4'b0110;
            4'b0110 : idelay_reset_cnt <= 4'b0111;
            4'b0111 : idelay_reset_cnt <= 4'b1000;
            4'b1000 : idelay_reset_cnt <= 4'b1001;
            4'b1001 : idelay_reset_cnt <= 4'b1010;
            4'b1010 : idelay_reset_cnt <= 4'b1011;
            4'b1011 : idelay_reset_cnt <= 4'b1100;
            default : idelay_reset_cnt <= 4'b1100;
         endcase
         if (idelay_reset_cnt == 4'b1100) begin
            idelayctrl_reset  <= 1'b0;
         end
         else begin
            idelayctrl_reset  <= 1'b1;
         end
      end
   end
 
 
  //----------------------------------------------------------------------------
  // Reset circuitry associated with the MMCM
  //----------------------------------------------------------------------------
 
  assign gtx_mmcm_rst_in = glbl_rst | gtx_dcm_locked_edge;
 
  // Synchronise the async dcm_locked into the gtx_clk clock domain
   tri_mode_ethernet_mac_0_sync_block lock_sync (
     .clk                   (gtx_clk),
     .data_in               (gtx_dcm_locked),
     .data_out              (gtx_dcm_locked_sync)
  );
 
  // for the falling edge detect we want to force this at power on so init the flop to 1
  always @(posedge gtx_clk)
  begin
     gtx_dcm_locked_reg     <= gtx_dcm_locked_sync;
     gtx_dcm_locked_edge    <= gtx_dcm_locked_reg & !gtx_dcm_locked_sync;
  end
 
  // the MMCM reset should be at least 5ns - that is one cycle of the input clock -
  // since the source of the input reset is unknown (a push switch in board design)
  // this needs to be debounced
   tri_mode_ethernet_mac_0_reset_sync gtx_mmcm_reset_gen (
      .clk                  (gtx_clk),
      .enable               (1'b1),
      .reset_in             (gtx_mmcm_rst_in),
      .reset_out            (gtx_mmcm_rst_out)
   );
 
 
endmodule