Subversion Repositories 2d_game_console

module Interrupt_Controller(
 
mem_q,
cpu_ack,
mem_grant,
clock,
reset,
int_req_0,
int_req_1,
int_req_2,
int_req_3,
 
 
mem_addr,
mem_wren,
mem_req,
isr_addr,
cpu_req,
int_mask,
current_state,
next_state,
int_ack_0,
int_ack_1,
int_ack_2,
int_ack_3
 
);
 
 
input		[15:0]	mem_q;
input 	mem_grant;
input 	cpu_ack;
input		int_req_0;
input		int_req_1;
input		int_req_2;
input		int_req_3;
input 	clock;
input 	reset;
 
 
output reg	[15:0]	int_mask;
output reg	[15:0]	isr_addr;
output reg	[15:0]	mem_addr;
output reg	mem_wren;
output reg	mem_req;
output reg	cpu_req;
output reg	int_ack_0;
output reg	int_ack_1;
output reg	int_ack_2;
output reg	int_ack_3;
 
 
/*########################################################################*/
/*########################  FINITE STATE MACHINE  ########################*/
/*########################  INTERRUPT CONTROLLER  ########################*/
/*########################################################################*/
 
output reg	[3:0]		current_state;
output reg	[3:0]		next_state;
 
// States
parameter	Idle			= 4'b0000;	// Idle			= 0
parameter	Read_Mask	= 4'b0001;	// Read_Mask	= 1
parameter	Wait_Mem_1	= 4'b0010;	// Wait_Mem_1	= 2
parameter	Wait_Mem_2	= 4'b0011;	// Wait_Mem_2	= 3
parameter	Get_Mask		= 4'b0100;	// Get_Mask		= 4
parameter	Int_Req_0	= 4'b0101;	// Int_Req_0	= 5
parameter	Int_Req_1	= 4'b0110;	// Int_Req_1	= 6
parameter	Int_Req_2	= 4'b0111;	// Int_Req_2	= 7
parameter	Int_Req_3	= 4'b1000;	// Int_Req_3	= 8
parameter	Wait_Req_0	= 4'b1001;	// Wait_Req_0	= 9
parameter	Wait_Req_1	= 4'b1010;	// Wait_Req_1	= 10
parameter	Wait_Req_2	= 4'b1011;	// Wait_Req_2	= 11
parameter	Wait_Req_3	= 4'b1100;	// Wait_Req_3	= 12
 
 
// Next State Decoder
always @ (*)
begin
	case (current_state)
 
		// State 0
		Idle:
		begin
			if ( (int_req_0 || int_req_1 || int_req_2 || int_req_3) && (!cpu_ack) )
				next_state = Read_Mask;
			else
				next_state = Idle;
		end
 
		// State 1
		Read_Mask:
		begin
			if (mem_grant)
				next_state = Wait_Mem_1;
			else
				next_state = Read_Mask;
		end
 
		// State 2
		Wait_Mem_1:
		begin
			next_state = Wait_Mem_2;
		end
 
		// State 3
		Wait_Mem_2:
		begin
			next_state = Get_Mask;
		end
 
		// State 4
		Get_Mask:
		begin
			if (int_mask[0] && int_req_0)
				next_state = Int_Req_0;
 
			else if (int_mask[1] && int_req_1)
				next_state = Int_Req_1;
 
			else if (int_mask[2] && int_req_2)
				next_state = Int_Req_2;
 
			else if (int_mask[3] && int_req_3)
				next_state = Int_Req_3;
 
			else
				next_state = Idle;
		end
 
		// State 5
		Int_Req_0:
		begin
			if (cpu_ack)
				next_state = Wait_Req_0;
			else
				next_state = Int_Req_0;
		end
 
		// State 6
		Int_Req_1:
		begin
			if (cpu_ack)
				next_state = Wait_Req_1;
			else
				next_state = Int_Req_1;
		end
 
		// State 7
		Int_Req_2:
		begin
			if (cpu_ack)
				next_state = Wait_Req_2;
			else
				next_state = Int_Req_2;
		end
 
		// State 8
		Int_Req_3:
		begin
			if (cpu_ack)
				next_state = Wait_Req_3;
			else
				next_state = Int_Req_3;
		end
 
		// State 9
		Wait_Req_0:
		begin
			if (cpu_ack || int_req_0)
				next_state = Wait_Req_0;
			else
				next_state = Idle;
		end
 
		// State 10
		Wait_Req_1:
		begin
			if (cpu_ack || int_req_1)
				next_state = Wait_Req_1;
			else
				next_state = Idle;
		end
 
		// State 11
		Wait_Req_2:
		begin
			if (cpu_ack || int_req_2)
				next_state = Wait_Req_2;
			else
				next_state = Idle;
		end
 
		// State 12
		Wait_Req_3:
		begin
			if (cpu_ack || int_req_3)
				next_state = Wait_Req_3;
			else
				next_state = Idle;
		end
 
		default:
		begin
			next_state = Idle;
		end
 
	endcase
 
end
 
 
// Output Decoder
always @ (*)
begin
 
	// Default Assignments
	mem_addr = 16'd1024;
	mem_wren = 0;
	mem_req = 0;
	int_ack_0 = 0;
	int_ack_1 = 0;
	int_ack_2 = 0;
	int_ack_3 = 0;
	cpu_req = 0;
	isr_addr = 16'd0;
 
 
	case (current_state)
 
		// State 0
		Idle:
		begin
 
		end
 
		// State 1
		Read_Mask:
		begin
			mem_req = 1;
		end
 
		// State 2
		Wait_Mem_1:
		begin
			mem_req = 1;
		end
 
		// State 3
		Wait_Mem_2:
		begin
			mem_req = 1;
		end
 
		// State 4
		Get_Mask:
		begin
			mem_req = 1;
		end
 
		// State 5
		Int_Req_0:
		begin
			cpu_req = 1;
			isr_addr = 16'd0;
		end
 
		// State 6
		Int_Req_1:
		begin
			cpu_req = 1;
			isr_addr = 16'd1;
		end
 
		// State 7
		Int_Req_2:
		begin
			cpu_req = 1;
			isr_addr = 16'd2;
		end
 
		// State 8
		Int_Req_3:
		begin
			cpu_req = 1;
			isr_addr = 16'd3;
		end
 
		// State 9
		Wait_Req_0:
		begin
			int_ack_0 = 1;
		end
 
		// State 10
		Wait_Req_1:
		begin
			int_ack_1 = 1;
		end
 
		// State 11
		Wait_Req_2:
		begin
			int_ack_2 = 1;
		end
 
		// State 12
		Wait_Req_3:
		begin
			int_ack_3 = 1;
		end
 
		default:
		begin
 
		end
 
	endcase
end
 
 
// State Register and Reset Logic
always @ (posedge clock)
begin
 
	if (reset)
	begin
		current_state	<= Idle;
	end
 
	else
	begin
		current_state	<=	next_state;
 
		// State: Get_Mask
		if (next_state == Get_Mask)
			int_mask <= mem_q;
 
	end
 
end
 
/*########################################################################*/
/*########################################################################*/
 
 
endmodule