Subversion Repositories 2d_game_console

C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_SUB.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_SUB.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity IP_SUB
-- Compiling architecture SYN of ip_sub

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Reset_Synchronizer.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Reset_Synchronizer.v
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
-- Compiling module Reset_Synchronizer

Top level modules:
        Reset_Synchronizer

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor.v
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
-- Compiling module Processor

Top level modules:
        Processor

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Memory_Arbiter.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Memory_Arbiter.v
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
-- Compiling module Memory_Arbiter

Top level modules:
        Memory_Arbiter

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ROM_Program.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ROM_Program.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package altera_mf_components
-- Compiling entity IP_ROM_Program
-- Compiling architecture SYN of ip_rom_program

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_DIVIDE.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_DIVIDE.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity IP_DIVIDE
-- Compiling architecture SYN of ip_divide

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/SRAM_Interface.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/SRAM_Interface.v
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
-- Compiling module SRAM_Interface

Top level modules:
        SRAM_Interface

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor_Controller.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Processor_Controller.v
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
-- Compiling module Processor_Controller

Top level modules:
        Processor_Controller

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_PLL.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_PLL.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity IP_PLL
-- Compiling architecture SYN of ip_pll

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ADD.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_ADD.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity IP_ADD
-- Compiling architecture SYN of ip_add

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/VGA_Interface.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/VGA_Interface.v
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
-- Compiling module VGA_Interface

Top level modules:
        VGA_Interface

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Processor.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Processor.v
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
-- Compiling module Sprite_Processor

Top level modules:
        Sprite_Processor

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_MULT.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_MULT.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity IP_MULT
-- Compiling architecture SYN of ip_mult

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Genesis_6button_Interface.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Genesis_6button_Interface.v
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
-- Compiling module Genesis_6button_Interface

Top level modules:
        Genesis_6button_Interface

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Interrupt_Controller.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Interrupt_Controller.v
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
-- Compiling module Interrupt_Controller

Top level modules:
        Interrupt_Controller

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Shape_Reader.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/Sprite_Shape_Reader.v
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
-- Compiling module Sprite_Shape_Reader

Top level modules:
        Sprite_Shape_Reader

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_COMPARE.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_COMPARE.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity IP_COMPARE
-- Compiling architecture SYN of ip_compare

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/TB_Processor.v {1 {vlog -work work -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/TB_Processor.v
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
-- Compiling module TB_Processor

Top level modules:
        TB_Processor

} {} {}} C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_RAM_Data.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/Lucas/Desktop/TCC/Processor_ModelSim/IP_RAM_Data.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package altera_mf_components
-- Compiling entity IP_RAM_Data
-- Compiling architecture SYN of ip_ram_data

} {} {}}