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[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [Memory_Arbiter.v] - Rev 2
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module Memory_Arbiter( clock, reset, addr_7, data_7, wren_7, req_7, addr_6, data_6, wren_6, req_6, addr_5, data_5, wren_5, req_5, addr_4, data_4, wren_4, req_4, addr_3, data_3, wren_3, req_3, addr_2, data_2, wren_2, req_2, addr_1, data_1, wren_1, req_1, addr_0, data_0, wren_0, req_0, grant_7, grant_6, grant_5, grant_4, grant_3, grant_2, grant_1, grant_0, addr, data, wren, current_state, next_state ); input [15:0] addr_0; input [15:0] addr_1; input [15:0] addr_2; input [15:0] addr_3; input [15:0] addr_4; input [15:0] addr_5; input [15:0] addr_6; input [15:0] addr_7; input [15:0] data_0; input [15:0] data_1; input [15:0] data_2; input [15:0] data_3; input [15:0] data_4; input [15:0] data_5; input [15:0] data_6; input [15:0] data_7; input wren_0; input wren_1; input wren_2; input wren_3; input wren_4; input wren_5; input wren_6; input wren_7; input req_0; input req_1; input req_2; input req_3; input req_4; input req_5; input req_6; input req_7; input clock; input reset; output reg [15:0] addr; output reg [15:0] data; output reg wren; output reg grant_0; output reg grant_1; output reg grant_2; output reg grant_3; output reg grant_4; output reg grant_5; output reg grant_6; output reg grant_7; /*########################################################################*/ /*######################## FINITE STATE MACHINE ########################*/ /*######################## MEMORY ARBITER ########################*/ /*########################################################################*/ output reg [3:0] current_state; output reg [3:0] next_state; // States parameter Idle = 4'b0000; // Idle = 0 parameter Grant_0 = 4'b0001; // Grant_0 = 1 parameter Grant_1 = 4'b0010; // Grant_1 = 2 parameter Grant_2 = 4'b0011; // Grant_2 = 3 parameter Grant_3 = 4'b0100; // Grant_3 = 4 parameter Grant_4 = 4'b0101; // Grant_4 = 5 parameter Grant_5 = 4'b0110; // Grant_5 = 6 parameter Grant_6 = 4'b0111; // Grant_6 = 7 parameter Grant_7 = 4'b1000; // Grant_7 = 8 // Next State Decoder always @ (*) begin case (current_state) // State 0 Idle: begin if (req_0) next_state = Grant_0; else if (req_1) next_state = Grant_1; else if (req_2) next_state = Grant_2; else if (req_3) next_state = Grant_3; else if (req_4) next_state = Grant_4; else if (req_5) next_state = Grant_5; else if (req_6) next_state = Grant_6; else if (req_7) next_state = Grant_7; else next_state = Idle; end // State 1 Grant_0: begin if (req_0) next_state = Grant_0; else next_state = Idle; end // State 2 Grant_1: begin if (req_1) next_state = Grant_1; else next_state = Idle; end // State 3 Grant_2: begin if (req_2) next_state = Grant_2; else next_state = Idle; end // State 4 Grant_3: begin if (req_3) next_state = Grant_3; else next_state = Idle; end // State 5 Grant_4: begin if (req_4) next_state = Grant_4; else next_state = Idle; end // State 6 Grant_5: begin if (req_5) next_state = Grant_5; else next_state = Idle; end // State 7 Grant_6: begin if (req_6) next_state = Grant_6; else next_state = Idle; end // State 8 Grant_7: begin if (req_7) next_state = Grant_7; else next_state = Idle; end default: begin next_state = Idle; end endcase end // Output Decoder always @ (*) begin // Default Assignments addr = addr_0; data = data_0; wren = 0; grant_0 = 0; grant_1 = 0; grant_2 = 0; grant_3 = 0; grant_4 = 0; grant_5 = 0; grant_6 = 0; grant_7 = 0; case (current_state) // State 0 Idle: begin end // State 1 Grant_0: begin addr = addr_0; data = data_0; wren = wren_0; grant_0 = 1; end // State 2 Grant_1: begin addr = addr_1; data = data_1; wren = wren_1; grant_1 = 1; end // State 3 Grant_2: begin addr = addr_2; data = data_2; wren = wren_2; grant_2 = 1; end // State 4 Grant_3: begin addr = addr_3; data = data_3; wren = wren_3; grant_3 = 1; end // State 5 Grant_4: begin addr = addr_4; data = data_4; wren = wren_4; grant_4 = 1; end // State 6 Grant_5: begin addr = addr_5; data = data_5; wren = wren_5; grant_5 = 1; end // State 7 Grant_6: begin addr = addr_6; data = data_6; wren = wren_6; grant_6 = 1; end // State 8 Grant_7: begin addr = addr_7; data = data_7; wren = wren_7; grant_7 = 1; end default: begin end endcase end // State Register and Reset Logic always @ (posedge clock) begin if (reset) begin current_state <= Idle; end else begin current_state <= next_state; end end /*########################################################################*/ /*########################################################################*/ endmodule