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[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [db/] [add_sub_mdk.tdf] - Rev 2
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--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="SIGNED" LPM_WIDTH=16 ONE_INPUT_IS_CONSTANT="NO" clock dataa datab overflow result
--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ VERSION_END
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Intel and sold by Intel or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
--synthesis_resources = lut 17
SUBDESIGN add_sub_mdk
(
clock : input;
dataa[15..0] : input;
datab[15..0] : input;
overflow : output;
result[15..0] : output;
)
VARIABLE
pipeline_dffe[15..0] : DFFE
WITH (
power_up ="low"
);
overflow_dffe[15..0] : DFFE
WITH (
power_up ="low"
);
result_int[15..0] : WIRE;
BEGIN
result_int[] = dataa[] + datab[];
pipeline_dffe[].clk = clock;
overflow_dffe[].clk = clock;
result[] = pipeline_dffe[15..0].q;
pipeline_dffe[15..0].d = result_int[];
overflow = overflow_dffe[0..0].q;
overflow_dffe[0].d = ! (dataa[15] $ datab[15]) & (dataa[15] $ result_int[15]);
END;
--VALID FILE