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--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" LOW_POWER_MODE="AUTO" NUMWORDS_A=6 NUMWORDS_B=6 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=4 WIDTH_B=4 WIDTH_BYTEENA_A=1 WIDTHAD_A=3 WIDTHAD_B=3 address_a address_b clock0 clocken0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ  VERSION_END


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FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);

--synthesis_resources = M9K 1 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_4b81
( 
        address_a[2..0] :       input;
        address_b[2..0] :       input;
        clock0  :       input;
        clocken0        :       input;
        data_a[3..0]    :       input;
        q_b[3..0]       :       output;
        wren_a  :       input;
) 
VARIABLE 
        ram_block3a0 : cycloneive_ram_block
                WITH (
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
                        CLK0_INPUT_CLOCK_ENABLE = "ena0",
                        CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
                        CONNECTIVITY_CHECKING = "OFF",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
                        OPERATION_MODE = "dual_port",
                        PORT_A_ADDRESS_WIDTH = 3,
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 0,
                        PORT_A_LAST_ADDRESS = 5,
                        PORT_A_LOGICAL_RAM_DEPTH = 6,
                        PORT_A_LOGICAL_RAM_WIDTH = 4,
                        PORT_B_ADDRESS_CLEAR = "none",
                        PORT_B_ADDRESS_CLOCK = "clock0",
                        PORT_B_ADDRESS_WIDTH = 3,
                        PORT_B_DATA_OUT_CLEAR = "none",
                        PORT_B_DATA_OUT_CLOCK = "clock0",
                        PORT_B_DATA_WIDTH = 1,
                        PORT_B_FIRST_ADDRESS = 0,
                        PORT_B_FIRST_BIT_NUMBER = 0,
                        PORT_B_LAST_ADDRESS = 5,
                        PORT_B_LOGICAL_RAM_DEPTH = 6,
                        PORT_B_LOGICAL_RAM_WIDTH = 4,
                        PORT_B_READ_ENABLE_CLOCK = "clock0",
                        RAM_BLOCK_TYPE = "AUTO"
                );
        ram_block3a1 : cycloneive_ram_block
                WITH (
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
                        CLK0_INPUT_CLOCK_ENABLE = "ena0",
                        CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
                        CONNECTIVITY_CHECKING = "OFF",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
                        OPERATION_MODE = "dual_port",
                        PORT_A_ADDRESS_WIDTH = 3,
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 1,
                        PORT_A_LAST_ADDRESS = 5,
                        PORT_A_LOGICAL_RAM_DEPTH = 6,
                        PORT_A_LOGICAL_RAM_WIDTH = 4,
                        PORT_B_ADDRESS_CLEAR = "none",
                        PORT_B_ADDRESS_CLOCK = "clock0",
                        PORT_B_ADDRESS_WIDTH = 3,
                        PORT_B_DATA_OUT_CLEAR = "none",
                        PORT_B_DATA_OUT_CLOCK = "clock0",
                        PORT_B_DATA_WIDTH = 1,
                        PORT_B_FIRST_ADDRESS = 0,
                        PORT_B_FIRST_BIT_NUMBER = 1,
                        PORT_B_LAST_ADDRESS = 5,
                        PORT_B_LOGICAL_RAM_DEPTH = 6,
                        PORT_B_LOGICAL_RAM_WIDTH = 4,
                        PORT_B_READ_ENABLE_CLOCK = "clock0",
                        RAM_BLOCK_TYPE = "AUTO"
                );
        ram_block3a2 : cycloneive_ram_block
                WITH (
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
                        CLK0_INPUT_CLOCK_ENABLE = "ena0",
                        CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
                        CONNECTIVITY_CHECKING = "OFF",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
                        OPERATION_MODE = "dual_port",
                        PORT_A_ADDRESS_WIDTH = 3,
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 2,
                        PORT_A_LAST_ADDRESS = 5,
                        PORT_A_LOGICAL_RAM_DEPTH = 6,
                        PORT_A_LOGICAL_RAM_WIDTH = 4,
                        PORT_B_ADDRESS_CLEAR = "none",
                        PORT_B_ADDRESS_CLOCK = "clock0",
                        PORT_B_ADDRESS_WIDTH = 3,
                        PORT_B_DATA_OUT_CLEAR = "none",
                        PORT_B_DATA_OUT_CLOCK = "clock0",
                        PORT_B_DATA_WIDTH = 1,
                        PORT_B_FIRST_ADDRESS = 0,
                        PORT_B_FIRST_BIT_NUMBER = 2,
                        PORT_B_LAST_ADDRESS = 5,
                        PORT_B_LOGICAL_RAM_DEPTH = 6,
                        PORT_B_LOGICAL_RAM_WIDTH = 4,
                        PORT_B_READ_ENABLE_CLOCK = "clock0",
                        RAM_BLOCK_TYPE = "AUTO"
                );
        ram_block3a3 : cycloneive_ram_block
                WITH (
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
                        CLK0_INPUT_CLOCK_ENABLE = "ena0",
                        CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
                        CONNECTIVITY_CHECKING = "OFF",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
                        OPERATION_MODE = "dual_port",
                        PORT_A_ADDRESS_WIDTH = 3,
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 3,
                        PORT_A_LAST_ADDRESS = 5,
                        PORT_A_LOGICAL_RAM_DEPTH = 6,
                        PORT_A_LOGICAL_RAM_WIDTH = 4,
                        PORT_B_ADDRESS_CLEAR = "none",
                        PORT_B_ADDRESS_CLOCK = "clock0",
                        PORT_B_ADDRESS_WIDTH = 3,
                        PORT_B_DATA_OUT_CLEAR = "none",
                        PORT_B_DATA_OUT_CLOCK = "clock0",
                        PORT_B_DATA_WIDTH = 1,
                        PORT_B_FIRST_ADDRESS = 0,
                        PORT_B_FIRST_BIT_NUMBER = 3,
                        PORT_B_LAST_ADDRESS = 5,
                        PORT_B_LOGICAL_RAM_DEPTH = 6,
                        PORT_B_LOGICAL_RAM_WIDTH = 4,
                        PORT_B_READ_ENABLE_CLOCK = "clock0",
                        RAM_BLOCK_TYPE = "AUTO"
                );
        address_a_wire[2..0]    : WIRE;
        address_b_wire[2..0]    : WIRE;

BEGIN 
        ram_block3a[3..0].clk0 = clock0;
        ram_block3a[3..0].ena0 = clocken0;
        ram_block3a[3..0].portaaddr[] = ( address_a_wire[2..0]);
        ram_block3a[0].portadatain[] = ( data_a[0..0]);
        ram_block3a[1].portadatain[] = ( data_a[1..1]);
        ram_block3a[2].portadatain[] = ( data_a[2..2]);
        ram_block3a[3].portadatain[] = ( data_a[3..3]);
        ram_block3a[3..0].portawe = wren_a;
        ram_block3a[3..0].portbaddr[] = ( address_b_wire[2..0]);
        ram_block3a[3..0].portbre = B"1111";
        address_a_wire[] = address_a[];
        address_b_wire[] = address_b[];
        q_b[] = ( ram_block3a[3..0].portbdataout[0..0]);
END;
--VALID FILE