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[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [db/] [altsyncram_jer3.tdf] - Rev 2
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--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_ACLR_B="NONE" BYTEENA_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_ECC="FALSE" ENABLE_RUNTIME_MOD="NO" IMPLEMENT_IN_LES="OFF" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK1" INIT_FILE="program.mif" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=2048 NUMWORDS_B=0 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" stratixiv_m144k_allow_dual_clocks="ON" WIDTH_A=32 WIDTH_B=1 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCSTATUS=3 WIDTHAD_A=11 WIDTHAD_B=1 WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END-- Copyright (C) 2017 Intel Corporation. All rights reserved.-- Your use of Intel Corporation's design tools, logic functions-- and other software and tools, and its AMPP partner logic-- functions, and any output files from any of the foregoing-- (including device programming or simulation files), and any-- associated documentation or information are expressly subject-- to the terms and conditions of the Intel Program License-- Subscription Agreement, the Intel Quartus Prime License Agreement,-- the Intel MegaCore Function License Agreement, or other-- applicable license agreement, including, without limitation,-- that your use is for the sole purpose of programming logic-- devices manufactured by Intel and sold by Intel or its-- authorized distributors. Please refer to the applicable-- agreement for further details.FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);--synthesis_resources = M9K 8OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";SUBDESIGN altsyncram_jer3(address_a[10..0] : input;clock0 : input;q_a[31..0] : output;)VARIABLEram_block1a0 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a1 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a2 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a3 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a4 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a5 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a6 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a7 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a8 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a9 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a10 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a11 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a12 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a13 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a14 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a15 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a16 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 16,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a17 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 17,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a18 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 18,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a19 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 19,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a20 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 20,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a21 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 21,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a22 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 22,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a23 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 23,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a24 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 24,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a25 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 25,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a26 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 26,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a27 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 27,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a28 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 28,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a29 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 29,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a30 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 30,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a31 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "none",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 11,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 31,PORT_A_LAST_ADDRESS = 2047,PORT_A_LOGICAL_RAM_DEPTH = 2048,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");address_a_wire[10..0] : WIRE;BEGINram_block1a[31..0].clk0 = clock0;ram_block1a[31..0].portaaddr[] = ( address_a_wire[10..0]);ram_block1a[31..0].portare = B"11111111111111111111111111111111";address_a_wire[] = address_a[];q_a[] = ( ram_block1a[31..0].portadataout[0..0]);END;--VALID FILE