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[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [db/] [altsyncram_jgr3.tdf] - Rev 2
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--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_ACLR_B="NONE" BYTEENA_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_ECC="FALSE" ENABLE_RUNTIME_MOD="NO" IMPLEMENT_IN_LES="OFF" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK1" INIT_FILE="program.mif" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=65536 NUMWORDS_B=0 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" stratixiv_m144k_allow_dual_clocks="ON" WIDTH_A=32 WIDTH_B=1 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCSTATUS=3 WIDTHAD_A=16 WIDTHAD_B=1 WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END-- Copyright (C) 2017 Intel Corporation. All rights reserved.-- Your use of Intel Corporation's design tools, logic functions-- and other software and tools, and its AMPP partner logic-- functions, and any output files from any of the foregoing-- (including device programming or simulation files), and any-- associated documentation or information are expressly subject-- to the terms and conditions of the Intel Program License-- Subscription Agreement, the Intel Quartus Prime License Agreement,-- the Intel MegaCore Function License Agreement, or other-- applicable license agreement, including, without limitation,-- that your use is for the sole purpose of programming logic-- devices manufactured by Intel and sold by Intel or its-- authorized distributors. Please refer to the applicable-- agreement for further details.FUNCTION decode_k8a (data[2..0])RETURNS ( eq[7..0]);FUNCTION mux_oob (data[255..0], sel[2..0])RETURNS ( result[31..0]);FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);--synthesis_resources = lut 168 M9K 256 reg 6OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";SUBDESIGN altsyncram_jgr3(address_a[15..0] : input;clock0 : input;q_a[31..0] : output;)VARIABLEaddress_reg_a[2..0] : dffe;out_address_reg_a[2..0] : dffe;rden_decode : decode_k8a;mux2 : mux_oob;ram_block1a0 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a1 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a2 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a3 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a4 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a5 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a6 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a7 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a8 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a9 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a10 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a11 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a12 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a13 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a14 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a15 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a16 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 16,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a17 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 17,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a18 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 18,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a19 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 19,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a20 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 20,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a21 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 21,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a22 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 22,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a23 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 23,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a24 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 24,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a25 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 25,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a26 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 26,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a27 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 27,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a28 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 28,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a29 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 29,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a30 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 30,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a31 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 31,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a32 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a33 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a34 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a35 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a36 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a37 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a38 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a39 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a40 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a41 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a42 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a43 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a44 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a45 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a46 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a47 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a48 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 16,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a49 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 17,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a50 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 18,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a51 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 19,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a52 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 20,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a53 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 21,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a54 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 22,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a55 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 23,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a56 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 24,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a57 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 25,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a58 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 26,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a59 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 27,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a60 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 28,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a61 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 29,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a62 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 30,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a63 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 31,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a64 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a65 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a66 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a67 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a68 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a69 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a70 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a71 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a72 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a73 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a74 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a75 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a76 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a77 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a78 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a79 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a80 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 16,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a81 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 17,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a82 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 18,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a83 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 19,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a84 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 20,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a85 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 21,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a86 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 22,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a87 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 23,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a88 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 24,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a89 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 25,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a90 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 26,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a91 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 27,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a92 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 28,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a93 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 29,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a94 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 30,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a95 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 31,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a96 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a97 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a98 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a99 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a100 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a101 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a102 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a103 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a104 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a105 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a106 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a107 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a108 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a109 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a110 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a111 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a112 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 16,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a113 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 17,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a114 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 18,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a115 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 19,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a116 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 20,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a117 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 21,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a118 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 22,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a119 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 23,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a120 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 24,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a121 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 25,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a122 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 26,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a123 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 27,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a124 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 28,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a125 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 29,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a126 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 30,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a127 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 31,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a128 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a129 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a130 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a131 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a132 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a133 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a134 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a135 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a136 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a137 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a138 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a139 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a140 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a141 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a142 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a143 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a144 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 16,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a145 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 17,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a146 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 18,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a147 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 19,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a148 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 20,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a149 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 21,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a150 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 22,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a151 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 23,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a152 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 24,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a153 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 25,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a154 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 26,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a155 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 27,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a156 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 28,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a157 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 29,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a158 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 30,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a159 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 31,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a160 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a161 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a162 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a163 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a164 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a165 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a166 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a167 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a168 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a169 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a170 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a171 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a172 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a173 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a174 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a175 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a176 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 16,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a177 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 17,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a178 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 18,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a179 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 19,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a180 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 20,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a181 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 21,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a182 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 22,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a183 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 23,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a184 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 24,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a185 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 25,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a186 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 26,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a187 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 27,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a188 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 28,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a189 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 29,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a190 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 30,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a191 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 31,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a192 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a193 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a194 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a195 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a196 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a197 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a198 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a199 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a200 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a201 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a202 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a203 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a204 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a205 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a206 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a207 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a208 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 16,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a209 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 17,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a210 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 18,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a211 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 19,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a212 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 20,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a213 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 21,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a214 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 22,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a215 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 23,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a216 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 24,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a217 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 25,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a218 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 26,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a219 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 27,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a220 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 28,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a221 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 29,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a222 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 30,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a223 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 31,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a224 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a225 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a226 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a227 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a228 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a229 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a230 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a231 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a232 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a233 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a234 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a235 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a236 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a237 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a238 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a239 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a240 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 16,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a241 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 17,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a242 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 18,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a243 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 19,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a244 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 20,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a245 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 21,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a246 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 22,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a247 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 23,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a248 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 24,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a249 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 25,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a250 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 26,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a251 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 27,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a252 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 28,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a253 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 29,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a254 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 30,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a255 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "program.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "rom",PORT_A_ADDRESS_CLEAR = "none",PORT_A_ADDRESS_WIDTH = 13,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 31,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 32,POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");address_a_sel[2..0] : WIRE;address_a_wire[15..0] : WIRE;rden_decode_addr_sel_a[2..0] : WIRE;BEGINaddress_reg_a[].clk = clock0;address_reg_a[].d = address_a_sel[];out_address_reg_a[].clk = clock0;out_address_reg_a[].d = address_reg_a[].q;rden_decode.data[] = rden_decode_addr_sel_a[];mux2.data[] = ( ram_block1a[255..0].portadataout[0..0]);mux2.sel[] = out_address_reg_a[].q;ram_block1a[255..0].clk0 = clock0;ram_block1a[255..0].ena0 = ( rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0]);ram_block1a[255..0].portaaddr[] = ( address_a_wire[12..0]);ram_block1a[255..0].portare = B"1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111";address_a_sel[2..0] = address_a[15..13];address_a_wire[] = address_a[];q_a[] = mux2.result[];rden_decode_addr_sel_a[2..0] = address_a_wire[15..13];END;--VALID FILE