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[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [db/] [altsyncram_q4s3.tdf] - Rev 2
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--altsyncram ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_ACLR_B="NONE" BYTEENA_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_ECC="FALSE" ENABLE_RUNTIME_MOD="NO" IMPLEMENT_IN_LES="OFF" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK1" INIT_FILE="sprite_shape.mif" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=65536 NUMWORDS_B=0 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" stratixiv_m144k_allow_dual_clocks="ON" WIDTH_A=16 WIDTH_B=1 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCSTATUS=3 WIDTHAD_A=16 WIDTHAD_B=1 WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END-- Copyright (C) 2017 Intel Corporation. All rights reserved.-- Your use of Intel Corporation's design tools, logic functions-- and other software and tools, and its AMPP partner logic-- functions, and any output files from any of the foregoing-- (including device programming or simulation files), and any-- associated documentation or information are expressly subject-- to the terms and conditions of the Intel Program License-- Subscription Agreement, the Intel Quartus Prime License Agreement,-- the Intel MegaCore Function License Agreement, or other-- applicable license agreement, including, without limitation,-- that your use is for the sole purpose of programming logic-- devices manufactured by Intel and sold by Intel or its-- authorized distributors. Please refer to the applicable-- agreement for further details.FUNCTION decode_rsa (data[2..0], enable)RETURNS ( eq[7..0]);FUNCTION decode_k8a (data[2..0])RETURNS ( eq[7..0]);FUNCTION mux_qob (data[127..0], sel[2..0])RETURNS ( result[15..0]);FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);--synthesis_resources = M9K 128 reg 6OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";SUBDESIGN altsyncram_q4s3(address_a[15..0] : input;clock0 : input;data_a[15..0] : input;q_a[15..0] : output;wren_a : input;)VARIABLEaddress_reg_a[2..0] : dffe;out_address_reg_a[2..0] : dffe;decode3 : decode_rsa;rden_decode : decode_k8a;mux2 : mux_qob;ram_block1a0 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a1 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a2 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a3 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a4 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a5 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a6 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a7 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a8 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a9 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a10 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a11 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a12 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a13 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a14 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a15 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 8191,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a16 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a17 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a18 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a19 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a20 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a21 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a22 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a23 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a24 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a25 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a26 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a27 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a28 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a29 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a30 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a31 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 8192,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 16383,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a32 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a33 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a34 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a35 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a36 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a37 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a38 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a39 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a40 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a41 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a42 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a43 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a44 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a45 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a46 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a47 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 16384,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 24575,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a48 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a49 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a50 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a51 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a52 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a53 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a54 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a55 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a56 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a57 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a58 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a59 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a60 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a61 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a62 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a63 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 24576,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 32767,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a64 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a65 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a66 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a67 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a68 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a69 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a70 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a71 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a72 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a73 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a74 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a75 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a76 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a77 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a78 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a79 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 32768,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 40959,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a80 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a81 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a82 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a83 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a84 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a85 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a86 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a87 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a88 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a89 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a90 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a91 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a92 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a93 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a94 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a95 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 40960,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 49151,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a96 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a97 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a98 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a99 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a100 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a101 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a102 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a103 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a104 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a105 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a106 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a107 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a108 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a109 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a110 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a111 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 49152,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 57343,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a112 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a113 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a114 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a115 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a116 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a117 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a118 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a119 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a120 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a121 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a122 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a123 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a124 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 12,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a125 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 13,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a126 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 14,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");ram_block1a127 : cycloneive_ram_blockWITH (CLK0_CORE_CLOCK_ENABLE = "ena0",CLK0_INPUT_CLOCK_ENABLE = "none",CLK0_OUTPUT_CLOCK_ENABLE = "none",CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "sprite_shape.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 13,PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,PORT_A_BYTE_SIZE = 1,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "clock0",PORT_A_DATA_WIDTH = 1,PORT_A_FIRST_ADDRESS = 57344,PORT_A_FIRST_BIT_NUMBER = 15,PORT_A_LAST_ADDRESS = 65535,PORT_A_LOGICAL_RAM_DEPTH = 65536,PORT_A_LOGICAL_RAM_WIDTH = 16,PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",POWER_UP_UNINITIALIZED = "false",RAM_BLOCK_TYPE = "AUTO");address_a_sel[2..0] : WIRE;address_a_wire[15..0] : WIRE;rden_decode_addr_sel_a[2..0] : WIRE;w_addr_val_a3w[2..0] : WIRE;w_addr_val_a4w[2..0] : WIRE;BEGINaddress_reg_a[].clk = clock0;address_reg_a[].d = address_a_sel[];out_address_reg_a[].clk = clock0;out_address_reg_a[].d = address_reg_a[].q;decode3.data[] = w_addr_val_a3w[];decode3.enable = wren_a;rden_decode.data[] = w_addr_val_a4w[];mux2.data[] = ( ram_block1a[127..0].portadataout[0..0]);mux2.sel[] = out_address_reg_a[].q;ram_block1a[127..0].clk0 = clock0;ram_block1a[127..0].ena0 = ( rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..7], rden_decode.eq[7..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..6], rden_decode.eq[6..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..5], rden_decode.eq[5..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..4], rden_decode.eq[4..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0]);ram_block1a[127..0].portaaddr[] = ( address_a_wire[12..0]);ram_block1a[0].portadatain[] = ( data_a[0..0]);ram_block1a[1].portadatain[] = ( data_a[1..1]);ram_block1a[2].portadatain[] = ( data_a[2..2]);ram_block1a[3].portadatain[] = ( data_a[3..3]);ram_block1a[4].portadatain[] = ( data_a[4..4]);ram_block1a[5].portadatain[] = ( data_a[5..5]);ram_block1a[6].portadatain[] = ( data_a[6..6]);ram_block1a[7].portadatain[] = ( data_a[7..7]);ram_block1a[8].portadatain[] = ( data_a[8..8]);ram_block1a[9].portadatain[] = ( data_a[9..9]);ram_block1a[10].portadatain[] = ( data_a[10..10]);ram_block1a[11].portadatain[] = ( data_a[11..11]);ram_block1a[12].portadatain[] = ( data_a[12..12]);ram_block1a[13].portadatain[] = ( data_a[13..13]);ram_block1a[14].portadatain[] = ( data_a[14..14]);ram_block1a[15].portadatain[] = ( data_a[15..15]);ram_block1a[16].portadatain[] = ( data_a[0..0]);ram_block1a[17].portadatain[] = ( data_a[1..1]);ram_block1a[18].portadatain[] = ( data_a[2..2]);ram_block1a[19].portadatain[] = ( data_a[3..3]);ram_block1a[20].portadatain[] = ( data_a[4..4]);ram_block1a[21].portadatain[] = ( data_a[5..5]);ram_block1a[22].portadatain[] = ( data_a[6..6]);ram_block1a[23].portadatain[] = ( data_a[7..7]);ram_block1a[24].portadatain[] = ( data_a[8..8]);ram_block1a[25].portadatain[] = ( data_a[9..9]);ram_block1a[26].portadatain[] = ( data_a[10..10]);ram_block1a[27].portadatain[] = ( data_a[11..11]);ram_block1a[28].portadatain[] = ( data_a[12..12]);ram_block1a[29].portadatain[] = ( data_a[13..13]);ram_block1a[30].portadatain[] = ( data_a[14..14]);ram_block1a[31].portadatain[] = ( data_a[15..15]);ram_block1a[32].portadatain[] = ( data_a[0..0]);ram_block1a[33].portadatain[] = ( data_a[1..1]);ram_block1a[34].portadatain[] = ( data_a[2..2]);ram_block1a[35].portadatain[] = ( data_a[3..3]);ram_block1a[36].portadatain[] = ( data_a[4..4]);ram_block1a[37].portadatain[] = ( data_a[5..5]);ram_block1a[38].portadatain[] = ( data_a[6..6]);ram_block1a[39].portadatain[] = ( data_a[7..7]);ram_block1a[40].portadatain[] = ( data_a[8..8]);ram_block1a[41].portadatain[] = ( data_a[9..9]);ram_block1a[42].portadatain[] = ( data_a[10..10]);ram_block1a[43].portadatain[] = ( data_a[11..11]);ram_block1a[44].portadatain[] = ( data_a[12..12]);ram_block1a[45].portadatain[] = ( data_a[13..13]);ram_block1a[46].portadatain[] = ( data_a[14..14]);ram_block1a[47].portadatain[] = ( data_a[15..15]);ram_block1a[48].portadatain[] = ( data_a[0..0]);ram_block1a[49].portadatain[] = ( data_a[1..1]);ram_block1a[50].portadatain[] = ( data_a[2..2]);ram_block1a[51].portadatain[] = ( data_a[3..3]);ram_block1a[52].portadatain[] = ( data_a[4..4]);ram_block1a[53].portadatain[] = ( data_a[5..5]);ram_block1a[54].portadatain[] = ( data_a[6..6]);ram_block1a[55].portadatain[] = ( data_a[7..7]);ram_block1a[56].portadatain[] = ( data_a[8..8]);ram_block1a[57].portadatain[] = ( data_a[9..9]);ram_block1a[58].portadatain[] = ( data_a[10..10]);ram_block1a[59].portadatain[] = ( data_a[11..11]);ram_block1a[60].portadatain[] = ( data_a[12..12]);ram_block1a[61].portadatain[] = ( data_a[13..13]);ram_block1a[62].portadatain[] = ( data_a[14..14]);ram_block1a[63].portadatain[] = ( data_a[15..15]);ram_block1a[64].portadatain[] = ( data_a[0..0]);ram_block1a[65].portadatain[] = ( data_a[1..1]);ram_block1a[66].portadatain[] = ( data_a[2..2]);ram_block1a[67].portadatain[] = ( data_a[3..3]);ram_block1a[68].portadatain[] = ( data_a[4..4]);ram_block1a[69].portadatain[] = ( data_a[5..5]);ram_block1a[70].portadatain[] = ( data_a[6..6]);ram_block1a[71].portadatain[] = ( data_a[7..7]);ram_block1a[72].portadatain[] = ( data_a[8..8]);ram_block1a[73].portadatain[] = ( data_a[9..9]);ram_block1a[74].portadatain[] = ( data_a[10..10]);ram_block1a[75].portadatain[] = ( data_a[11..11]);ram_block1a[76].portadatain[] = ( data_a[12..12]);ram_block1a[77].portadatain[] = ( data_a[13..13]);ram_block1a[78].portadatain[] = ( data_a[14..14]);ram_block1a[79].portadatain[] = ( data_a[15..15]);ram_block1a[80].portadatain[] = ( data_a[0..0]);ram_block1a[81].portadatain[] = ( data_a[1..1]);ram_block1a[82].portadatain[] = ( data_a[2..2]);ram_block1a[83].portadatain[] = ( data_a[3..3]);ram_block1a[84].portadatain[] = ( data_a[4..4]);ram_block1a[85].portadatain[] = ( data_a[5..5]);ram_block1a[86].portadatain[] = ( data_a[6..6]);ram_block1a[87].portadatain[] = ( data_a[7..7]);ram_block1a[88].portadatain[] = ( data_a[8..8]);ram_block1a[89].portadatain[] = ( data_a[9..9]);ram_block1a[90].portadatain[] = ( data_a[10..10]);ram_block1a[91].portadatain[] = ( data_a[11..11]);ram_block1a[92].portadatain[] = ( data_a[12..12]);ram_block1a[93].portadatain[] = ( data_a[13..13]);ram_block1a[94].portadatain[] = ( data_a[14..14]);ram_block1a[95].portadatain[] = ( data_a[15..15]);ram_block1a[96].portadatain[] = ( data_a[0..0]);ram_block1a[97].portadatain[] = ( data_a[1..1]);ram_block1a[98].portadatain[] = ( data_a[2..2]);ram_block1a[99].portadatain[] = ( data_a[3..3]);ram_block1a[100].portadatain[] = ( data_a[4..4]);ram_block1a[101].portadatain[] = ( data_a[5..5]);ram_block1a[102].portadatain[] = ( data_a[6..6]);ram_block1a[103].portadatain[] = ( data_a[7..7]);ram_block1a[104].portadatain[] = ( data_a[8..8]);ram_block1a[105].portadatain[] = ( data_a[9..9]);ram_block1a[106].portadatain[] = ( data_a[10..10]);ram_block1a[107].portadatain[] = ( data_a[11..11]);ram_block1a[108].portadatain[] = ( data_a[12..12]);ram_block1a[109].portadatain[] = ( data_a[13..13]);ram_block1a[110].portadatain[] = ( data_a[14..14]);ram_block1a[111].portadatain[] = ( data_a[15..15]);ram_block1a[112].portadatain[] = ( data_a[0..0]);ram_block1a[113].portadatain[] = ( data_a[1..1]);ram_block1a[114].portadatain[] = ( data_a[2..2]);ram_block1a[115].portadatain[] = ( data_a[3..3]);ram_block1a[116].portadatain[] = ( data_a[4..4]);ram_block1a[117].portadatain[] = ( data_a[5..5]);ram_block1a[118].portadatain[] = ( data_a[6..6]);ram_block1a[119].portadatain[] = ( data_a[7..7]);ram_block1a[120].portadatain[] = ( data_a[8..8]);ram_block1a[121].portadatain[] = ( data_a[9..9]);ram_block1a[122].portadatain[] = ( data_a[10..10]);ram_block1a[123].portadatain[] = ( data_a[11..11]);ram_block1a[124].portadatain[] = ( data_a[12..12]);ram_block1a[125].portadatain[] = ( data_a[13..13]);ram_block1a[126].portadatain[] = ( data_a[14..14]);ram_block1a[127].portadatain[] = ( data_a[15..15]);ram_block1a[127..0].portare = B"11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111";ram_block1a[127..0].portawe = ( decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4],decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]);address_a_sel[2..0] = address_a[15..13];address_a_wire[] = address_a[];q_a[] = mux2.result[];rden_decode_addr_sel_a[2..0] = address_a_wire[15..13];w_addr_val_a3w[2..0] = address_a_wire[15..13];w_addr_val_a4w[] = rden_decode_addr_sel_a[];END;--VALID FILE