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Subversion Repositories 2d_game_console
[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [db/] [cmpr_pgc.tdf] - Rev 2
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--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_WIDTH=3 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab
--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ VERSION_END
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Intel and sold by Intel or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
--synthesis_resources =
SUBDESIGN cmpr_pgc
(
aeb : output;
dataa[2..0] : input;
datab[2..0] : input;
)
VARIABLE
aeb_result_wire[0..0] : WIRE;
aneb_result_wire[0..0] : WIRE;
data_wire[7..0] : WIRE;
eq_wire : WIRE;
BEGIN
aeb = eq_wire;
aeb_result_wire[] = (! aneb_result_wire[]);
aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]);
data_wire[] = ( datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[6..6] $ data_wire[7..7]), ((data_wire[2..2] $ data_wire[3..3]) # (data_wire[4..4] $ data_wire[5..5])));
eq_wire = aeb_result_wire[];
END;
--VALID FILE