OpenCores
URL https://opencores.org/ocsvn/2d_game_console/2d_game_console/trunk

Subversion Repositories 2d_game_console

[/] [2d_game_console/] [trunk/] [Processor_Quartus/] [db/] [lpm_divide_1lr.tdf] - Rev 2

Compare with Previous | Blame | View Log

--lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_PIPELINE=1 LPM_REMAINDERPOSITIVE="FALSE" LPM_WIDTHD=16 LPM_WIDTHN=16 OPTIMIZE_FOR_SPEED=5 clock denom numer quotient remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_abs 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_divide 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ  VERSION_END


-- Copyright (C) 2017  Intel Corporation. All rights reserved.
--  Your use of Intel Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Intel Program License 
--  Subscription Agreement, the Intel Quartus Prime License Agreement,
--  the Intel MegaCore Function License Agreement, or other 
--  applicable license agreement, including, without limitation, 
--  that your use is for the sole purpose of programming logic 
--  devices manufactured by Intel and sold by Intel or its 
--  authorized distributors.  Please refer to the applicable 
--  agreement for further details.


FUNCTION abs_divider_lug (clock, denominator[15..0], numerator[15..0])
RETURNS ( quotient[15..0], remainder[15..0]);

--synthesis_resources = lut 211 reg 66 
SUBDESIGN lpm_divide_1lr
( 
        clock   :       input;
        denom[15..0]    :       input;
        numer[15..0]    :       input;
        quotient[15..0] :       output;
        remain[15..0]   :       output;
) 
VARIABLE 
        divider : abs_divider_lug;
        numer_tmp[15..0]        : WIRE;

BEGIN 
        divider.clock = clock;
        divider.denominator[] = denom[];
        divider.numerator[] = numer_tmp[];
        numer_tmp[] = numer[];
        quotient[] = divider.quotient[];
        remain[] = divider.remainder[];
END;
--VALID FILE

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.