Subversion Repositories 6809_6309_compatible_core

$date
        Fri Jan 23 08:52:46 2015
$end
$version
        Icarus Verilog
$end
$timescale
        1ns
$end
$scope module tb $end
$var wire 16 ! addr [15:0] $end
$var wire 16 " addr_o [15:0] $end
$var wire 8 # data_i [7:0] $end
$var wire 8 $ data_o [7:0] $end
$var wire 8 % data_o_o [7:0] $end
$var wire 1 & oe $end
$var wire 1 ' we $end
$var reg 1 ( clk $end
$var reg 1 ) firq $end
$var reg 1 * irq $end
$var reg 1 + nmi $end
$var reg 1 , reset $end
$scope module cpu $end
$var wire 8 - alu_o_CCR [7:0] $end
$var wire 16 . alu_o_result [15:0] $end
$var wire 16 / cpu_addr_o [15:0] $end
$var wire 1 0 cpu_clk $end
$var wire 8 1 cpu_data_i [7:0] $end
$var wire 8 2 cpu_data_o [7:0] $end
$var wire 1 3 cpu_dtack_i $end
$var wire 1 4 cpu_firq_n $end
$var wire 1 5 cpu_irq_n $end
$var wire 1 6 cpu_nmi_n $end
$var wire 1 & cpu_oe_o $end
$var wire 1 7 cpu_reset $end
$var wire 6 8 cpu_state_o [5:0] $end
$var wire 1 ' cpu_we_o $end
$var wire 1 9 debug_clk $end
$var wire 1 : debug_data_o $end
$var wire 2 ; dec_lo_dest_memtype [1:0] $end
$var wire 4 < dec_lo_dest_reg_addr [3:0] $end
$var wire 4 = dec_lo_left_path_addr [3:0] $end
$var wire 2 > dec_lo_left_path_memtype [1:0] $end
$var wire 4 ? dec_lo_right_path_addr [3:0] $end
$var wire 2 @ dec_lo_right_path_memtype [1:0] $end
$var wire 5 A dec_o_alu_opcode [4:0] $end
$var wire 1 B dec_o_alu_size $end
$var wire 1 C dec_o_cond_taken $end
$var wire 2 D dec_o_dest_memtype [1:0] $end
$var wire 1 E dec_o_ea_indirect $end
$var wire 1 F dec_o_ea_ofs16 $end
$var wire 1 G dec_o_ea_ofs5 $end
$var wire 1 H dec_o_ea_ofs8 $end
$var wire 1 I dec_o_ea_wpost $end
$var wire 4 J dec_o_eabase [3:0] $end
$var wire 4 K dec_o_eaidx [3:0] $end
$var wire 2 L dec_o_left_path_memtype [1:0] $end
$var wire 1 M dec_o_operand_read $end
$var wire 1 N dec_o_operand_write $end
$var wire 3 O dec_o_p1_mode [2:0] $end
$var wire 2 P dec_o_right_path_memtype [1:0] $end
$var wire 1 Q dec_o_source_size $end
$var wire 1 R dec_o_use_s $end
$var wire 1 S dec_o_wdest $end
$var wire 1 T dec_o_write_flags $end
$var wire 1 U k_firq_req $end
$var wire 1 V k_irq_req $end
$var wire 1 W k_nmi_req $end
$var wire 1 X k_reset $end
$var wire 1 Y op_CWAI $end
$var wire 1 Z op_EXG $end
$var wire 1 [ op_JMP $end
$var wire 1 \ op_JSR $end
$var wire 1 ] op_LEA $end
$var wire 1 ^ op_MUL $end
$var wire 1 _ op_PULL $end
$var wire 1 ` op_PUSH $end
$var wire 1 a op_RTI $end
$var wire 1 b op_RTS $end
$var wire 1 c op_SWI $end
$var wire 1 d op_SYNC $end
$var wire 1 e op_TFR $end
$var wire 8 f regs_o_CCR [7:0] $end
$var wire 8 g regs_o_dp [7:0] $end
$var wire 16 h regs_o_eamem_addr [15:0] $end
$var wire 16 i regs_o_left_path_data [15:0] $end
$var wire 16 j regs_o_pc [15:0] $end
$var wire 16 k regs_o_right_path_data [15:0] $end
$var wire 16 l regs_o_su [15:0] $end
$var reg 4 m datamux_o_alu_in_left_path_addr [3:0] $end
$var reg 16 n datamux_o_alu_in_left_path_data [15:0] $end
$var reg 16 o datamux_o_alu_in_right_path_data [15:0] $end
$var reg 16 p datamux_o_dest [15:0] $end
$var reg 4 q datamux_o_dest_reg_addr [3:0] $end
$var reg 1 r k_clear_e $end
$var reg 16 s k_cpu_addr [15:0] $end
$var reg 8 t k_cpu_data_o [7:0] $end
$var reg 1 u k_cpu_oe $end
$var reg 1 v k_cpu_we $end
$var reg 1 w k_dec_su $end
$var reg 8 x k_eahi [7:0] $end
$var reg 8 y k_ealo [7:0] $end
$var reg 1 z k_exception_process $end
$var reg 1 { k_force_read_word_from_mem $end
$var reg 1 | k_inc_pc $end
$var reg 1 } k_inc_su $end
$var reg 8 ~ k_ind_ea [7:0] $end
$var reg 1 !" k_indirect_loaded $end
$var reg 3 "" k_mem_state [2:0] $end
$var reg 8 #" k_memhi [7:0] $end
$var reg 8 $" k_memlo [7:0] $end
$var reg 1 %" k_mul_cnt $end
$var reg 16 &" k_new_pc [15:0] $end
$var reg 8 '" k_ofshi [7:0] $end
$var reg 8 (" k_ofslo [7:0] $end
$var reg 8 )" k_opcode [7:0] $end
$var reg 1 *" k_p2_valid $end
$var reg 1 +" k_p3_valid $end
$var reg 8 ," k_postbyte [7:0] $end
$var reg 4 -" k_pp_active_reg [3:0] $end
$var reg 8 ." k_pp_regs [7:0] $end
$var reg 3 /" k_reg_firq [2:0] $end
$var reg 3 0" k_reg_irq [2:0] $end
$var reg 3 1" k_reg_nmi [2:0] $end
$var reg 1 2" k_set_e $end
$var reg 1 3" k_write_dest $end
$var reg 1 4" k_write_exg $end
$var reg 1 5" k_write_pc $end
$var reg 1 6" k_write_post_incdec $end
$var reg 1 7" k_write_tfr $end
$var reg 6 8" next_mem_state [5:0] $end
$var reg 6 9" next_push_state [5:0] $end
$var reg 6 :" next_state [5:0] $end
$var reg 6 ;" state [5:0] $end
$scope module alu $end
$var wire 8 <" CCR [7:0] $end
$var wire 16 =" a_in [15:0] $end
$var wire 16 >" b_in [15:0] $end
$var wire 4 ?" ccr16_out [3:0] $end
$var wire 8 @" ccr8_out [7:0] $end
$var wire 1 0 clk_in $end
$var wire 5 A" opcode_in [4:0] $end
$var wire 16 B" q16_mul [15:0] $end
$var wire 16 C" q16_out [15:0] $end
$var wire 8 D" q8_out [7:0] $end
$var wire 1 B sz_in $end
$var reg 8 E" CCRo [7:0] $end
$var reg 16 F" q_out [15:0] $end
$var reg 16 G" ra_in [15:0] $end
$var reg 16 H" rb_in [15:0] $end
$var reg 5 I" rop_in [4:0] $end
$scope module mulu $end
$var wire 8 J" a [7:0] $end
$var wire 8 K" b [7:0] $end
$var wire 1 0 clk_in $end
$var wire 16 L" q [15:0] $end
$var reg 16 M" pipe0 [15:0] $end
$var reg 16 N" pipe1 [15:0] $end
$upscope $end
$scope module alu8 $end
$var wire 8 O" CCR [7:0] $end
$var wire 8 P" a_in [7:0] $end
$var wire 1 Q" arith_c $end
$var wire 1 R" arith_h $end
$var wire 8 S" arith_q [7:0] $end
$var wire 1 T" arith_v $end
$var wire 8 U" b_in [7:0] $end
$var wire 1 V" c_in $end
$var wire 1 W" ccom8_r $end
$var wire 1 X" cdaa8_r $end
$var wire 1 0 clk_in $end
$var wire 1 Y" cneg8_r $end
$var wire 8 Z" com8_r [7:0] $end
$var wire 8 [" com8_w [7:0] $end
$var wire 4 \" daa8h_r [3:0] $end
$var wire 8 ]" daa_p0_r [7:0] $end
$var wire 1 ^" h_in $end
$var wire 8 _" logic_q [7:0] $end
$var wire 1 `" n_in $end
$var wire 8 a" neg8_r [7:0] $end
$var wire 8 b" neg8_w [7:0] $end
$var wire 5 c" opcode_in [4:0] $end
$var wire 1 d" shift_c $end
$var wire 8 e" shift_q [7:0] $end
$var wire 1 f" shift_v $end
$var wire 1 g" v_in $end
$var wire 1 h" vcom8_r $end
$var wire 1 i" vneg8_r $end
$var wire 1 j" z_in $end
$var reg 8 k" CCRo [7:0] $end
$var reg 8 l" alu8_b_in [7:0] $end
$var reg 1 m" c8 $end
$var reg 1 n" h8 $end
$var reg 8 o" q8 [7:0] $end
$var reg 8 p" q_out [7:0] $end
$var reg 1 q" v8 $end
$scope module l8 $end
$var wire 8 r" a_in [7:0] $end
$var wire 8 s" b_in [7:0] $end
$var wire 2 t" opcode_in [1:0] $end
$var reg 8 u" q_out [7:0] $end
$upscope $end
$scope module a8 $end
$var wire 8 v" a_in [7:0] $end
$var wire 8 w" b_in [7:0] $end
$var wire 1 x" carry $end
$var wire 1 V" carry_in $end
$var wire 1 ^" half_c_in $end
$var wire 2 y" opcode_in [1:0] $end
$var reg 1 z" carry_out $end
$var reg 1 {" half_c_out $end
$var reg 1 |" overflow_out $end
$var reg 8 }" q_out [7:0] $end
$upscope $end
$scope module s8 $end
$var wire 8 ~" a_in [7:0] $end
$var wire 8 !# b_in [7:0] $end
$var wire 1 V" carry_in $end
$var wire 1 d" carry_out $end
$var wire 3 "# opcode_in [2:0] $end
$var wire 1 g" overflow_in $end
$var reg 1 ## overflow_out $end
$var reg 8 $# q_out [7:0] $end
$upscope $end
$upscope $end
$scope module alu16 $end
$var wire 8 %# CCR [7:0] $end
$var wire 16 &# a_in [15:0] $end
$var wire 1 '# arith_c $end
$var wire 16 (# arith_q [15:0] $end
$var wire 1 )# arith_v $end
$var wire 16 *# b_in [15:0] $end
$var wire 1 +# c_in $end
$var wire 1 0 clk_in $end
$var wire 1 ,# n_in $end
$var wire 5 -# opcode_in [4:0] $end
$var wire 16 .# q_mul_in [15:0] $end
$var wire 1 /# v_in $end
$var wire 1 0# z_in $end
$var reg 4 1# CCRo [3:0] $end
$var reg 1 2# c16 $end
$var reg 1 3# n16 $end
$var reg 16 4# q16 [15:0] $end
$var reg 16 5# q_out [15:0] $end
$var reg 1 6# reg_n_in $end
$var reg 1 7# reg_z_in $end
$var reg 1 8# v16 $end
$var reg 1 9# z16 $end
$scope module a16 $end
$var wire 16 :# a_in [15:0] $end
$var wire 16 ;# b_in [15:0] $end
$var wire 1 +# carry_in $end
$var wire 2 <# opcode_in [1:0] $end
$var reg 1 =# carry_out $end
$var reg 1 ># overflow_out $end
$var reg 16 ?# q_out [15:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module regs $end
$var wire 8 @# CCR_in [7:0] $end
$var wire 8 A# CCR_o [7:0] $end
$var wire 1 B# clear_e $end
$var wire 1 0 clk_in $end
$var wire 16 C# data_w [15:0] $end
$var wire 1 D# dec_su $end
$var wire 16 E# ea_reg_post [15:0] $end
$var wire 16 F# eamem_addr [15:0] $end
$var wire 16 G# eamem_addr_o [15:0] $end
$var wire 8 H# eapostbyte [7:0] $end
$var wire 4 I# exg_dest_r [3:0] $end
$var wire 1 J# inc_pc $end
$var wire 1 K# inc_su $end
$var wire 16 L# left [15:0] $end
$var wire 16 M# new_pc [15:0] $end
$var wire 16 N# offset16 [15:0] $end
$var wire 4 O# path_left_addr [3:0] $end
$var wire 4 P# path_right_addr [3:0] $end
$var wire 16 Q# pc_plus_1 [15:0] $end
$var wire 8 R# reg_dp [7:0] $end
$var wire 16 S# reg_pc [15:0] $end
$var wire 16 T# reg_su [15:0] $end
$var wire 16 U# right [15:0] $end
$var wire 4 V# right_reg [3:0] $end
$var wire 1 W# set_e $end
$var wire 1 R use_s $end
$var wire 1 X# write_exg $end
$var wire 1 Y# write_flags $end
$var wire 1 Z# write_pc $end
$var wire 1 [# write_post $end
$var wire 1 \# write_reg $end
$var wire 4 ]# write_reg_addr [3:0] $end
$var wire 1 ^# write_tfr $end
$var reg 8 _# ACCA [7:0] $end
$var reg 8 `# ACCB [7:0] $end
$var reg 8 a# DP [7:0] $end
$var reg 16 b# IX [15:0] $end
$var reg 16 c# IY [15:0] $end
$var reg 16 d# PC [15:0] $end
$var reg 16 e# SS [15:0] $end
$var reg 16 f# SU [15:0] $end
$var reg 1 g# cff $end
$var reg 1 h# eflag $end
$var reg 1 i# fflag $end
$var reg 1 j# hflag $end
$var reg 1 k# intff $end
$var reg 1 l# nff $end
$var reg 16 m# path_left_data [15:0] $end
$var reg 16 n# path_right_data [15:0] $end
$var reg 1 o# vff $end
$var reg 1 p# zff $end
$scope module ea $end
$var wire 8 q# acca [7:0] $end
$var wire 8 r# accb [7:0] $end
$var wire 16 s# ea_reg_post_o [15:0] $end
$var wire 16 t# eamem_addr_o [15:0] $end
$var wire 8 u# eapostbyte [7:0] $end
$var wire 16 v# ix [15:0] $end
$var wire 16 w# iy [15:0] $end
$var wire 16 x# offset16 [15:0] $end
$var wire 16 y# pc [15:0] $end
$var wire 16 z# s [15:0] $end
$var wire 16 {# u [15:0] $end
$var reg 16 |# ea_reg [15:0] $end
$var reg 16 }# ea_reg_post [15:0] $end
$var reg 16 ~# eamem_addr [15:0] $end
$upscope $end
$upscope $end
$scope module decs $end
$var wire 5 !$ alu_opcode [4:0] $end
$var wire 1 0 clk_in $end
$var wire 1 T dest_flags_o $end
$var wire 2 "$ dest_memtype_o [1:0] $end
$var wire 3 #$ mode [2:0] $end
$var wire 8 $$ opcode [7:0] $end
$var wire 1 M operand_read_o $end
$var wire 1 N operand_write_o $end
$var wire 1 %$ page2_valid $end
$var wire 1 &$ page3_valid $end
$var wire 2 '$ path_left_memtype_o [1:0] $end
$var wire 2 ($ path_right_memtype_o [1:0] $end
$var wire 8 )$ postbyte0 [7:0] $end
$var wire 1 B result_size $end
$var wire 1 Q source_size $end
$var wire 1 R use_s $end
$var wire 1 S write_dest $end
$var reg 5 *$ aop [4:0] $end
$var reg 2 +$ dest_memtype_lo [1:0] $end
$var reg 4 ,$ dest_reg_lo [3:0] $end
$var reg 2 -$ dm [1:0] $end
$var reg 4 .$ dr [3:0] $end
$var reg 2 /$ lm [1:0] $end
$var reg 4 0$ lr [3:0] $end
$var reg 3 1$ mo [2:0] $end
$var reg 1 2$ op_CWAI $end
$var reg 1 3$ op_EXG $end
$var reg 1 4$ op_JMP $end
$var reg 1 5$ op_JSR $end
$var reg 1 6$ op_LEA $end
$var reg 1 7$ op_MUL $end
$var reg 1 8$ op_PULL $end
$var reg 1 9$ op_PUSH $end
$var reg 1 :$ op_RTI $end
$var reg 1 ;$ op_RTS $end
$var reg 1 <$ op_SWI $end
$var reg 1 =$ op_SYNC $end
$var reg 1 >$ op_TFR $end
$var reg 1 ?$ p2 $end
$var reg 1 @$ p3 $end
$var reg 4 A$ path_left_addr_lo [3:0] $end
$var reg 2 B$ path_left_memtype_lo [1:0] $end
$var reg 4 C$ path_right_addr_lo [3:0] $end
$var reg 2 D$ path_right_memtype_lo [1:0] $end
$var reg 2 E$ rm [1:0] $end
$var reg 4 F$ rr [3:0] $end
$var reg 1 G$ ss $end
$var reg 1 H$ sz $end
$upscope $end
$scope module dec_ea $end
$var wire 1 E ea_is_indirect_o $end
$var wire 8 I$ eapostbyte [7:0] $end
$var reg 1 J$ ea_ofs16_o $end
$var reg 1 K$ ea_ofs5_o $end
$var reg 1 L$ ea_ofs8_o $end
$var reg 1 M$ ea_write_back_o $end
$var reg 4 N$ eabase_o [3:0] $end
$var reg 4 O$ eaindex_o [3:0] $end
$upscope $end
$scope module test_cond $end
$var wire 8 P$ CCR [7:0] $end
$var wire 8 Q$ op [7:0] $end
$var wire 8 R$ opcode [7:0] $end
$var wire 1 %$ page2_valid $end
$var wire 8 S$ postbyte0 [7:0] $end
$var reg 1 T$ cond_taken $end
$upscope $end
$upscope $end
$scope module imem $end
$var wire 16 U$ addr [15:0] $end
$var wire 8 V$ data_i [7:0] $end
$var wire 8 W$ data_o [7:0] $end
$var wire 8 X$ mem0 [7:0] $end
$var wire 8 Y$ mem1 [7:0] $end
$var wire 8 Z$ mem2 [7:0] $end
$var wire 8 [$ mem3 [7:0] $end
$var wire 1 \$ oe $end
$var wire 1 ]$ we $end
$var reg 8 ^$ latecheddata [7:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx ^$
1]$
1\$
b11111111 [$
b0 Z$
b11001110 Y$
b10000 X$
bx W$
bx V$
bx U$
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bx Q$
b0 P$
bx O$
bx N$
xM$
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bx I$
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bx F$
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bx B$
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x9$
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bx 1$
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bx ($
bx '$
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bx $$
bx #$
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bx ~#
bx }#
bx |#
b111000000000 {#
b111100000000 z#
b1111111111111110 y#
bx x#
b1010010101011010 w#
b0 v#
bx u#
bx t#
bx s#
bx r#
bx q#
0p#
0o#
b1111111111111111 n#
b1111111111111111 m#
0l#
0k#
0j#
0i#
0h#
0g#
b111000000000 f#
b111100000000 e#
b1111111111111110 d#
b1010010101011010 c#
b0 b#
b0 a#
bx `#
bx _#
0^#
bx ]#
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0Y#
0X#
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bx V#
b1111111111111111 U#
b111x00000000 T#
b1111111111111110 S#
b0 R#
b1111111111111111 Q#
bx P#
bx O#
bx N#
bx M#
b0 L#
xK#
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bx I#
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b0 C#
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b0 A#
b100 @#
bx ?#
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bx <#
bx ;#
bx :#
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b0 5#
b0 4#
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b100 1#
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b11111111 J"
bx I"
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b0 F"
b100 E"
b0 D"
b0 C"
bx B"
bx A"
b100 @"
b100 ?"
bx >"
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b0 <"
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bx :"
bx 9"
bx 8"
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b0 1"
b0 0"
b0 /"
bx ."
bx -"
bx ,"
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bx )"
bx ("
bx '"
bx &"
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bx $"
bx #"
b0 ""
0!"
bx ~
x}
x|
x{
xz
bx y
bx x
xw
0v
0u
bx t
bx s
xr
bx q
b0 p
bx o
b1111111111111111 n
bx m
b111x00000000 l
b1111111111111111 k
b1111111111111110 j
b1111111111111111 i
bx h
b0 g
b0 f
xe
xd
xc
xb
xa
x`
x_
x^
x]
x\
x[
xZ
xY
1X
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bx P
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bx D
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bx A
bx @
bx ?
bx >
bx =
bx <
bx ;
0:
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$end
#5
b0 \"
0X"
0i"
0W"
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1d"
b0 Z"
b0 ["
b11111111 $#
b11111111 e"
b101 ]"
b11111111 P"
b11111111 r"
b11111111 v"
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