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Subversion Repositories 6809_6309_compatible_core
[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809.srr] - Rev 12
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#Build: Synplify Pro I-2013.09L , Build 064R, Nov 15 2013#install: C:\lscc\diamond\3.1_x64\synpbase#OS: Windows 7 6.1#Hostname: ALE-PC#Implementation: P6809$ Start of Compile#Wed Jul 02 14:52:21 2014Synopsys Verilog Compiler, version comp201309rc, Build 136R, built Nov 18 2013@N|Running in 64-bit modeCopyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.@N:: Running Verilog Compiler in System Verilog mode@N:: Running Verilog Compiler in Multiple File Compilation Unit mode@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v"@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\pmi_def.v"@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\umr_capim.v"@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\scemi_objects.v"@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\scemi_pipes.svh"@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\hypermods.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v"@I:"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\defs.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\fontrom.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v"Verilog syntax check successful!Selecting top level module CC3_top@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":62:7:62:12|Synthesizing module logic8@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":85:7:85:12|Synthesizing module arith8@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":158:7:158:12|Synthesizing module shift8@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":198:7:198:10|Synthesizing module alu8@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":320:0:320:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":241:12:241:13|No assignment to n8@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":241:20:241:21|No assignment to z8@W: CL169 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":302:0:302:5|Pruning register regq8[7:0]@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":604:7:604:12|Synthesizing module mul8x8@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":129:7:129:13|Synthesizing module arith16@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":326:7:326:11|Synthesizing module alu16@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":412:23:412:29|No assignment to wire arith_h@W: CL169 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":518:0:518:5|Pruning register regq16[15:0]@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":15:7:15:9|Synthesizing module alu@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":191:7:191:13|Synthesizing module calc_ea@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":7:7:7:14|Synthesizing module regblock@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":9:7:9:17|Synthesizing module decode_regs@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":147:7:147:15|Synthesizing module decode_op@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":275:7:275:15|Synthesizing module decode_ea@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":301:7:301:16|Synthesizing module decode_alu@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":374:7:374:20|Synthesizing module test_condition@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu@N: CG793 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":455:6:455:13|Ignoring system task $display@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":1104:0:1104:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":69:11:69:23|No assignment to wire alu8_o_result@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":70:11:70:20|No assignment to wire alu8_o_CCR@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Register bit k_mem_dest[1] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Register bit next_mem_state[1] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Register bit next_mem_state[2] is always 0, optimizing ...@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Pruning register bits 2 to 1 of next_mem_state[5:0]@W: CL260 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Pruning register bit 1 of k_mem_dest[1:0]@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1291:7:1291:11|Synthesizing module DP8KC@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v":8:7:8:12|Synthesizing module bios2k@W: CL168 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\fontrom.v":8:7:8:13|Synthesizing module fontrom@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v":8:7:8:15|Synthesizing module textmem4k@W: CL168 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":2:7:2:13|Synthesizing module vgatext@N: CG793 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":133:4:133:11|Ignoring system task $display@N: CG512 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":167:6:167:11|System task $write is not supported yet@N: CG512 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":174:6:174:11|System task $write is not supported yet@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":184:0:184:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@W: CG781 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of redr[3:0] -- not in use ...@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...@N: CL177 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Sharing sequential element redr.@N: CL177 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Sharing sequential element greenr.@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":10:7:10:13|Synthesizing module CC3_top@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":37:14:37:21|No assignment to clk_div2@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":42:25:42:35|No assignment to wire cpu1_addr_o@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:40:43:51|No assignment to wire cpu1_data_in@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:54:43:66|No assignment to wire cpu1_data_out@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":44:23:44:29|No assignment to wire cpu1_we@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":44:32:44:38|No assignment to wire cpu1_oe@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:54:43:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":42:25:42:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":146:25:146:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Pruning register bits 5 to 3 of next_push_state[5:0]@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":22:12:22:20|Input debug_clk is unused@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":378:18:378:20|Input port bits 7 to 4 of CCR[7:0] are unused@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":303:18:303:26|Input port bits 5 to 4 of postbyte0[7:0] are unused@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":276:18:276:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":330:18:330:20|Input port bits 7 to 4 of CCR[7:0] are unused@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Pruning register bits 15 to 13 of pipe0[15:0]@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Register bit pipe0[12] is always 0, optimizing ...@W: CL260 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Pruning register bit 12 of pipe0[12:0]@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":199:12:199:17|Input clk_in is unused@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":160:18:160:21|Input b_in is unused@ENDAt c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 87MB peak: 100MB)Process took 0h:00m:02s realtime, 0h:00m:02s cputime# Wed Jul 02 14:52:24 2014###########################################################]Premap ReportSynopsys Lattice Technology Pre-mapping, Version maplat, Build 800R, Built Nov 18 2013 10:58:25Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.Product Version I-2013.09LMapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)@L: C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_scck.rptPrinting clock summary report in "C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_scck.rpt" file@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabledDesign Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB)syn_allowed_resources : blockrams=26 set on top level netlist CC3_topClock Summary**************Start Requested Requested Clock ClockClock Frequency Period Type Group----------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Autoconstr_clkgroup_0CC3_top|div_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Autoconstr_clkgroup_0======================================================================================================================@W: MT529 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 95 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.Pre-mapping successful!At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 146MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputime# Wed Jul 02 14:52:26 2014###########################################################]Map & Optimize ReportSynopsys Lattice Technology Mapper, Version maplat, Build 800R, Built Nov 18 2013 10:58:25Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.Product Version I-2013.09LMapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabledDesign Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)Available hyper_sources - for debug and ip modelsNone Found@N: MT206 |Auto Constrain mode is enabledFinished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputsFinished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 176MB peak: 176MB)@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputsFinished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 171MB peak: 179MB)Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 165MB peak: 183MB)@N: FA113 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":222:2:222:5|Pipelining module ea_reg_post_o[15:0]@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register IY[15:0] pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register IX[15:0] pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register DP[7:0] pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register ACCB[7:0] pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register eflag pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register fflag pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register hflag pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register intff pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register nff pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register zff pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register vff pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register cff pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register PC[15:0] pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register ACCA[7:0] pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Register k_write_pc pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Register k_inc_pc pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":35:0:35:5|Register ra_in[15:0] pushed in.@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]Starting Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 167MB peak: 183MB)Finished Early Timing Optimization (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 168MB peak: 183MB)Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 167MB peak: 183MB)Finished preparing to map (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 167MB peak: 183MB)Finished technology mapping (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 211MB peak: 241MB)Pass CPU time Worst Slack Luts / Registers------------------------------------------------------------Pass CPU time Worst Slack Luts / Registers------------------------------------------------------------1 0h:00m:16s -5.65ns 2081 / 5842 0h:00m:16s -5.65ns 2081 / 5843 0h:00m:16s -5.65ns 2081 / 584------------------------------------------------------------@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[3]" with 66 loads replicated 3 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[2]" with 58 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[7]" with 27 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[4]" with 19 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[3]" with 19 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[2]" with 17 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[0]" with 53 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[6]" with 49 loads replicated 3 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[7]" with 40 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[4]" with 37 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[5]" with 36 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[5]" with 25 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[6]" with 22 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[1]" with 53 loads replicated 3 times to improve timingTiming driven replication reportAdded 31 Registers via timing driven replicationAdded 0 LUTs via timing driven replication@N: FX271 :|Instance "cpu0.regs.IY_pipe_4" with 16 loads replicated 2 times to improve timing@N: FX271 :|Instance "cpu0.regs.IX_pipe_4" with 16 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_ind_ea[1]" with 28 loads replicated 1 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_ind_ea[7]" with 30 loads replicated 1 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_ind_ea[2]" with 23 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_ind_ea[0]" with 22 loads replicated 1 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[0]" with 19 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[1]" with 18 loads replicated 1 times to improve timingAdded 12 Registers via timing driven replicationAdded 0 LUTs via timing driven replication@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_ind_ea[3]" with 9 loads replicated 1 times to improve timing@N: FX271 :|Instance "cpu0.regs.IX_pipe_1" with 16 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.state[3]" with 61 loads replicated 2 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_ind_ea[6]" with 37 loads replicated 3 times to improve timing@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":35:0:35:5|Instance "cpu0.alu.rop_in[1]" with 59 loads replicated 2 times to improve timingAdded 10 Registers via timing driven replicationAdded 2 LUTs via timing driven replicationPass CPU time Worst Slack Luts / Registers------------------------------------------------------------1 0h:00m:18s -2.91ns 2131 / 6372 0h:00m:18s -2.91ns 2133 / 6373 0h:00m:18s -3.31ns 2134 / 6374 0h:00m:18s -2.91ns 2133 / 6375 0h:00m:18s -2.91ns 2134 / 637------------------------------------------------------------@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":64:10:64:33|Instance "textctrl.vsync_cnt_2_sqmuxa_i_0_o3" with 44 loads replicated 1 times to improve timingAdded 0 Registers via timing driven replicationAdded 1 LUTs via timing driven replicationPass CPU time Worst Slack Luts / Registers------------------------------------------------------------1 0h:00m:18s -2.95ns 2131 / 637------------------------------------------------------------Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 183MB peak: 241MB)@N: FX164 |The option to pack flops in the IOB has not been specifiedFinished restoring hierarchy (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:19s; Memory used current: 185MB peak: 241MB)#### START OF CLOCK OPTIMIZATION REPORT #####[1 non-gated/non-generated clock tree(s) driving 653 clock pin(s) of sequential element(s)0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)310 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks=========================== Non-Gated/Non-Generated Clocks ============================Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance---------------------------------------------------------------------------------------@K:CKID0001 clk40_i port 653 cpu_clk=======================================================================================##### END OF CLOCK OPTIMIZATION REPORT ######]Writing Analyst data base C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809.srmFinished Writing Netlist Databases (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:20s; Memory used current: 186MB peak: 241MB)Writing EDIF Netlist and constraint files@W: MT558 |Unable to locate source for clock CC3_top|div_derived_clock. Clock will not be forward annotatedI-2013.09L@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pFFinished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:21s; Memory used current: 191MB peak: 241MB)@W: MT420 |Found inferred clock CC3_top|clk40_i with period 13.64ns. Please declare a user-defined clock on object "p:clk40_i"Found clock CC3_top|cpu_clk_derived_clock with period 13.64ns##### START OF TIMING REPORT #####[# Timing Report written on Wed Jul 02 14:52:48 2014#Top view: CC3_topRequested Frequency: 73.3 MHzWire load mode: topPaths requested: 5Constraint File(s):@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.Performance Summary*******************Worst slack in design: -2.407Requested Estimated Requested Estimated Clock ClockStarting Clock Frequency Frequency Period Period Slack Type Group-------------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i 73.3 MHz 62.3 MHz 13.639 16.046 -2.407 inferred Autoconstr_clkgroup_0=========================================================================================================================Clock Relationships*******************Clocks | rise to rise | fall to fall | rise to fall | fall to rise-------------------------------------------------------------------------------------------------------------------------Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack-------------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i CC3_top|clk40_i | 13.639 -2.407 | No paths - | No paths - | No paths -=========================================================================================================================Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.Interface Information*********************No IO constraint found====================================Detailed Report for Clock: CC3_top|clk40_i====================================Starting Points with Worst Slack********************************Starting ArrivalInstance Reference Type Pin Net Time SlackClock-------------------------------------------------------------------------------------------------------------cpu0.regs.IX_pipe_4_fast CC3_top|clk40_i FD1P3AX Q IX_0_sqmuxaf_fast 1.108 -2.407cpu0.regs.IX_pipe_77 CC3_top|clk40_i FD1P3AX Q left_1f_0[0] 0.972 -2.271cpu0.regs.IX_pipe_78 CC3_top|clk40_i FD1P3AX Q ea_reg_postf_0[0] 0.972 -2.271cpu0.k_ind_ea_fast[1] CC3_top|clk40_i FD1P3AX Q k_ind_ea_fast[1] 1.180 -2.166cpu0.k_ind_ea_fast[0] CC3_top|clk40_i FD1P3AX Q k_ind_ea_fast[0] 1.148 -2.134cpu0.regs.IY_pipe_4_fast CC3_top|clk40_i FD1P3AX Q IY_1_sqmuxaf_fast 1.148 -2.096cpu0.k_ind_ea_fast[2] CC3_top|clk40_i FD1P3AX Q k_ind_ea_fast[2] 1.044 -2.030cpu0.regs.IX_pipe_4_rep1 CC3_top|clk40_i FD1P3AX Q IX_0_sqmuxaf_rep1 1.180 -1.985cpu0.regs.IY_pipe_4_rep1 CC3_top|clk40_i FD1P3AX Q IY_1_sqmuxaf_rep1 1.180 -1.985cpu0.regs.IX_pipe_67 CC3_top|clk40_i FD1P3AX Q left_1f_0[2] 0.972 -1.920=============================================================================================================Ending Points with Worst Slack******************************Starting RequiredInstance Reference Type Pin Net Time SlackClock----------------------------------------------------------------------------------------------cpu0.regs.SS[13] CC3_top|clk40_i FD1P3AX D SS_lm[13] 13.728 -2.407cpu0.regs.SU[13] CC3_top|clk40_i FD1P3AX D SU_lm[13] 13.728 -2.407cpu0.regs.SS[7] CC3_top|clk40_i FD1P3AX D SS_lm[7] 13.728 -1.555cpu0.regs.SU[7] CC3_top|clk40_i FD1P3AX D SU_lm[7] 13.728 -1.555cpu0.regs.SS[10] CC3_top|clk40_i FD1P3AX D SS_lm[10] 13.728 -1.553cpu0.regs.SU[10] CC3_top|clk40_i FD1P3AX D SU_lm[10] 13.728 -1.553cpu0.regs.SS[9] CC3_top|clk40_i FD1P3AX D SS_lm[9] 13.728 -1.299cpu0.regs.SU[9] CC3_top|clk40_i FD1P3AX D SU_lm[9] 13.728 -1.299cpu0.regs.SS[6] CC3_top|clk40_i FD1P3AX D SS_lm[6] 13.728 -1.204cpu0.regs.SU[6] CC3_top|clk40_i FD1P3AX D SU_lm[6] 13.728 -1.204==============================================================================================Worst Path Information***********************Path information for path number 1:Requested Period: 13.639- Setup time: -0.089+ Clock delay at ending point: 0.000 (ideal)= Required time: 13.728- Propagation time: 16.134- Clock delay at starting point: 0.000 (ideal)= Slack (critical) : -2.407Number of logic level(s): 20Starting point: cpu0.regs.IX_pipe_4_fast / QEnding point: cpu0.regs.SS[13] / DThe start point is clocked by CC3_top|clk40_i [rising] on pin CKThe end point is clocked by CC3_top|clk40_i [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)--------------------------------------------------------------------------------------------------------cpu0.regs.IX_pipe_4_fast FD1P3AX Q Out 1.108 1.108 -IX_0_sqmuxaf_fast Net - - - - 3cpu0.regs.IX_10_0[0] ORCALUT4 A In 0.000 1.108 -cpu0.regs.IX_10_0[0] ORCALUT4 Z Out 1.017 2.125 -N_631 Net - - - - 1cpu0.regs.IX_10[0] ORCALUT4 B In 0.000 2.125 -cpu0.regs.IX_10[0] ORCALUT4 Z Out 1.153 3.277 -IX[0] Net - - - - 3cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 B In 0.000 3.277 -cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 Z Out 1.017 4.294 -ea_reg_3_am[0] Net - - - - 1cpu0.regs.ea.ea_reg_3[0] PFUMX BLUT In 0.000 4.294 -cpu0.regs.ea.ea_reg_3[0] PFUMX Z Out 0.422 4.716 -ea_reg[0] Net - - - - 5cpu0.regs.ea.un1_pc_0[0] ORCALUT4 A In 0.000 4.716 -cpu0.regs.ea.un1_pc_0[0] ORCALUT4 Z Out 1.089 5.805 -N_72 Net - - - - 2cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D C1 In 0.000 5.805 -cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D COUT Out 1.545 7.350 -eamem_addr_o_cry_0 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D CIN In 0.000 7.350 -cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D COUT Out 0.143 7.492 -eamem_addr_o_cry_2 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D CIN In 0.000 7.492 -cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D COUT Out 0.143 7.635 -eamem_addr_o_cry_4 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D CIN In 0.000 7.635 -cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D COUT Out 0.143 7.778 -eamem_addr_o_cry_6 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D CIN In 0.000 7.778 -cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D COUT Out 0.143 7.921 -eamem_addr_o_cry_8 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D CIN In 0.000 7.921 -cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D COUT Out 0.143 8.064 -eamem_addr_o_cry_10 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D CIN In 0.000 8.064 -cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D COUT Out 0.143 8.207 -eamem_addr_o_cry_12 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D CIN In 0.000 8.207 -cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D S0 Out 1.725 9.931 -regs_o_eamem_addr[13] Net - - - - 4cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 D In 0.000 9.931 -cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 Z Out 1.017 10.948 -datamux_o_dest_6[13] Net - - - - 1cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 B In 0.000 10.948 -cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 Z Out 1.017 11.965 -datamux_o_dest_am[13] Net - - - - 1cpu0.regs.ea.datamux_o_dest[13] PFUMX BLUT In 0.000 11.965 -cpu0.regs.ea.datamux_o_dest[13] PFUMX Z Out 0.286 12.251 -datamux_o_dest[13] Net - - - - 2cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 B In 0.000 12.251 -cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 Z Out 1.233 13.484 -left_1[13] Net - - - - 6cpu0.regs.SS_16_0[13] ORCALUT4 B In 0.000 13.484 -cpu0.regs.SS_16_0[13] ORCALUT4 Z Out 1.017 14.501 -N_258 Net - - - - 1cpu0.regs.SS_16[13] ORCALUT4 A In 0.000 14.501 -cpu0.regs.SS_16[13] ORCALUT4 Z Out 1.017 15.518 -SS_16[13] Net - - - - 1cpu0.regs.SS_lm_0[13] ORCALUT4 A In 0.000 15.518 -cpu0.regs.SS_lm_0[13] ORCALUT4 Z Out 0.617 16.134 -SS_lm[13] Net - - - - 1cpu0.regs.SS[13] FD1P3AX D In 0.000 16.134 -========================================================================================================Path information for path number 2:Requested Period: 13.639- Setup time: -0.089+ Clock delay at ending point: 0.000 (ideal)= Required time: 13.728- Propagation time: 16.134- Clock delay at starting point: 0.000 (ideal)= Slack (critical) : -2.407Number of logic level(s): 20Starting point: cpu0.regs.IX_pipe_4_fast / QEnding point: cpu0.regs.SU[13] / DThe start point is clocked by CC3_top|clk40_i [rising] on pin CKThe end point is clocked by CC3_top|clk40_i [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)--------------------------------------------------------------------------------------------------------cpu0.regs.IX_pipe_4_fast FD1P3AX Q Out 1.108 1.108 -IX_0_sqmuxaf_fast Net - - - - 3cpu0.regs.IX_10_0[0] ORCALUT4 A In 0.000 1.108 -cpu0.regs.IX_10_0[0] ORCALUT4 Z Out 1.017 2.125 -N_631 Net - - - - 1cpu0.regs.IX_10[0] ORCALUT4 B In 0.000 2.125 -cpu0.regs.IX_10[0] ORCALUT4 Z Out 1.153 3.277 -IX[0] Net - - - - 3cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 B In 0.000 3.277 -cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 Z Out 1.017 4.294 -ea_reg_3_am[0] Net - - - - 1cpu0.regs.ea.ea_reg_3[0] PFUMX BLUT In 0.000 4.294 -cpu0.regs.ea.ea_reg_3[0] PFUMX Z Out 0.422 4.716 -ea_reg[0] Net - - - - 5cpu0.regs.ea.un1_pc_0[0] ORCALUT4 A In 0.000 4.716 -cpu0.regs.ea.un1_pc_0[0] ORCALUT4 Z Out 1.089 5.805 -N_72 Net - - - - 2cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D C1 In 0.000 5.805 -cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D COUT Out 1.545 7.350 -eamem_addr_o_cry_0 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D CIN In 0.000 7.350 -cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D COUT Out 0.143 7.492 -eamem_addr_o_cry_2 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D CIN In 0.000 7.492 -cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D COUT Out 0.143 7.635 -eamem_addr_o_cry_4 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D CIN In 0.000 7.635 -cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D COUT Out 0.143 7.778 -eamem_addr_o_cry_6 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D CIN In 0.000 7.778 -cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D COUT Out 0.143 7.921 -eamem_addr_o_cry_8 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D CIN In 0.000 7.921 -cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D COUT Out 0.143 8.064 -eamem_addr_o_cry_10 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D CIN In 0.000 8.064 -cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D COUT Out 0.143 8.207 -eamem_addr_o_cry_12 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D CIN In 0.000 8.207 -cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D S0 Out 1.725 9.931 -regs_o_eamem_addr[13] Net - - - - 4cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 D In 0.000 9.931 -cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 Z Out 1.017 10.948 -datamux_o_dest_6[13] Net - - - - 1cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 B In 0.000 10.948 -cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 Z Out 1.017 11.965 -datamux_o_dest_am[13] Net - - - - 1cpu0.regs.ea.datamux_o_dest[13] PFUMX BLUT In 0.000 11.965 -cpu0.regs.ea.datamux_o_dest[13] PFUMX Z Out 0.286 12.251 -datamux_o_dest[13] Net - - - - 2cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 B In 0.000 12.251 -cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 Z Out 1.233 13.484 -left_1[13] Net - - - - 6cpu0.regs.SU_16_0[13] ORCALUT4 B In 0.000 13.484 -cpu0.regs.SU_16_0[13] ORCALUT4 Z Out 1.017 14.501 -N_294 Net - - - - 1cpu0.regs.SU_16[13] ORCALUT4 A In 0.000 14.501 -cpu0.regs.SU_16[13] ORCALUT4 Z Out 1.017 15.518 -SU_16[13] Net - - - - 1cpu0.regs.SU_lm_0[13] ORCALUT4 A In 0.000 15.518 -cpu0.regs.SU_lm_0[13] ORCALUT4 Z Out 0.617 16.134 -SU_lm[13] Net - - - - 1cpu0.regs.SU[13] FD1P3AX D In 0.000 16.134 -========================================================================================================Path information for path number 3:Requested Period: 13.639- Setup time: -0.089+ Clock delay at ending point: 0.000 (ideal)= Required time: 13.728- Propagation time: 15.999- Clock delay at starting point: 0.000 (ideal)= Slack (non-critical) : -2.271Number of logic level(s): 20Starting point: cpu0.regs.IX_pipe_77 / QEnding point: cpu0.regs.SS[13] / DThe start point is clocked by CC3_top|clk40_i [rising] on pin CKThe end point is clocked by CC3_top|clk40_i [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)--------------------------------------------------------------------------------------------------------cpu0.regs.IX_pipe_77 FD1P3AX Q Out 0.972 0.972 -left_1f_0[0] Net - - - - 1cpu0.regs.IX_10_0[0] ORCALUT4 C In 0.000 0.972 -cpu0.regs.IX_10_0[0] ORCALUT4 Z Out 1.017 1.989 -N_631 Net - - - - 1cpu0.regs.IX_10[0] ORCALUT4 B In 0.000 1.989 -cpu0.regs.IX_10[0] ORCALUT4 Z Out 1.153 3.141 -IX[0] Net - - - - 3cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 B In 0.000 3.141 -cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 Z Out 1.017 4.158 -ea_reg_3_am[0] Net - - - - 1cpu0.regs.ea.ea_reg_3[0] PFUMX BLUT In 0.000 4.158 -cpu0.regs.ea.ea_reg_3[0] PFUMX Z Out 0.422 4.580 -ea_reg[0] Net - - - - 5cpu0.regs.ea.un1_pc_0[0] ORCALUT4 A In 0.000 4.580 -cpu0.regs.ea.un1_pc_0[0] ORCALUT4 Z Out 1.089 5.669 -N_72 Net - - - - 2cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D C1 In 0.000 5.669 -cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D COUT Out 1.545 7.214 -eamem_addr_o_cry_0 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D CIN In 0.000 7.214 -cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D COUT Out 0.143 7.356 -eamem_addr_o_cry_2 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D CIN In 0.000 7.356 -cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D COUT Out 0.143 7.499 -eamem_addr_o_cry_4 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D CIN In 0.000 7.499 -cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D COUT Out 0.143 7.642 -eamem_addr_o_cry_6 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D CIN In 0.000 7.642 -cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D COUT Out 0.143 7.785 -eamem_addr_o_cry_8 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D CIN In 0.000 7.785 -cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D COUT Out 0.143 7.928 -eamem_addr_o_cry_10 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D CIN In 0.000 7.928 -cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D COUT Out 0.143 8.070 -eamem_addr_o_cry_12 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D CIN In 0.000 8.070 -cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D S0 Out 1.725 9.796 -regs_o_eamem_addr[13] Net - - - - 4cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 D In 0.000 9.796 -cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 Z Out 1.017 10.812 -datamux_o_dest_6[13] Net - - - - 1cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 B In 0.000 10.812 -cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 Z Out 1.017 11.829 -datamux_o_dest_am[13] Net - - - - 1cpu0.regs.ea.datamux_o_dest[13] PFUMX BLUT In 0.000 11.829 -cpu0.regs.ea.datamux_o_dest[13] PFUMX Z Out 0.286 12.115 -datamux_o_dest[13] Net - - - - 2cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 B In 0.000 12.115 -cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 Z Out 1.233 13.348 -left_1[13] Net - - - - 6cpu0.regs.SS_16_0[13] ORCALUT4 B In 0.000 13.348 -cpu0.regs.SS_16_0[13] ORCALUT4 Z Out 1.017 14.365 -N_258 Net - - - - 1cpu0.regs.SS_16[13] ORCALUT4 A In 0.000 14.365 -cpu0.regs.SS_16[13] ORCALUT4 Z Out 1.017 15.382 -SS_16[13] Net - - - - 1cpu0.regs.SS_lm_0[13] ORCALUT4 A In 0.000 15.382 -cpu0.regs.SS_lm_0[13] ORCALUT4 Z Out 0.617 15.999 -SS_lm[13] Net - - - - 1cpu0.regs.SS[13] FD1P3AX D In 0.000 15.999 -========================================================================================================Path information for path number 4:Requested Period: 13.639- Setup time: -0.089+ Clock delay at ending point: 0.000 (ideal)= Required time: 13.728- Propagation time: 15.999- Clock delay at starting point: 0.000 (ideal)= Slack (non-critical) : -2.271Number of logic level(s): 20Starting point: cpu0.regs.IX_pipe_78 / QEnding point: cpu0.regs.SS[13] / DThe start point is clocked by CC3_top|clk40_i [rising] on pin CKThe end point is clocked by CC3_top|clk40_i [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)--------------------------------------------------------------------------------------------------------cpu0.regs.IX_pipe_78 FD1P3AX Q Out 0.972 0.972 -ea_reg_postf_0[0] Net - - - - 1cpu0.regs.IX_10_0[0] ORCALUT4 B In 0.000 0.972 -cpu0.regs.IX_10_0[0] ORCALUT4 Z Out 1.017 1.989 -N_631 Net - - - - 1cpu0.regs.IX_10[0] ORCALUT4 B In 0.000 1.989 -cpu0.regs.IX_10[0] ORCALUT4 Z Out 1.153 3.141 -IX[0] Net - - - - 3cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 B In 0.000 3.141 -cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 Z Out 1.017 4.158 -ea_reg_3_am[0] Net - - - - 1cpu0.regs.ea.ea_reg_3[0] PFUMX BLUT In 0.000 4.158 -cpu0.regs.ea.ea_reg_3[0] PFUMX Z Out 0.422 4.580 -ea_reg[0] Net - - - - 5cpu0.regs.ea.un1_pc_0[0] ORCALUT4 A In 0.000 4.580 -cpu0.regs.ea.un1_pc_0[0] ORCALUT4 Z Out 1.089 5.669 -N_72 Net - - - - 2cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D C1 In 0.000 5.669 -cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D COUT Out 1.545 7.214 -eamem_addr_o_cry_0 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D CIN In 0.000 7.214 -cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D COUT Out 0.143 7.356 -eamem_addr_o_cry_2 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D CIN In 0.000 7.356 -cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D COUT Out 0.143 7.499 -eamem_addr_o_cry_4 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D CIN In 0.000 7.499 -cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D COUT Out 0.143 7.642 -eamem_addr_o_cry_6 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D CIN In 0.000 7.642 -cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D COUT Out 0.143 7.785 -eamem_addr_o_cry_8 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D CIN In 0.000 7.785 -cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D COUT Out 0.143 7.928 -eamem_addr_o_cry_10 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D CIN In 0.000 7.928 -cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D COUT Out 0.143 8.070 -eamem_addr_o_cry_12 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D CIN In 0.000 8.070 -cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D S0 Out 1.725 9.796 -regs_o_eamem_addr[13] Net - - - - 4cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 D In 0.000 9.796 -cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 Z Out 1.017 10.812 -datamux_o_dest_6[13] Net - - - - 1cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 B In 0.000 10.812 -cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 Z Out 1.017 11.829 -datamux_o_dest_am[13] Net - - - - 1cpu0.regs.ea.datamux_o_dest[13] PFUMX BLUT In 0.000 11.829 -cpu0.regs.ea.datamux_o_dest[13] PFUMX Z Out 0.286 12.115 -datamux_o_dest[13] Net - - - - 2cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 B In 0.000 12.115 -cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 Z Out 1.233 13.348 -left_1[13] Net - - - - 6cpu0.regs.SS_16_0[13] ORCALUT4 B In 0.000 13.348 -cpu0.regs.SS_16_0[13] ORCALUT4 Z Out 1.017 14.365 -N_258 Net - - - - 1cpu0.regs.SS_16[13] ORCALUT4 A In 0.000 14.365 -cpu0.regs.SS_16[13] ORCALUT4 Z Out 1.017 15.382 -SS_16[13] Net - - - - 1cpu0.regs.SS_lm_0[13] ORCALUT4 A In 0.000 15.382 -cpu0.regs.SS_lm_0[13] ORCALUT4 Z Out 0.617 15.999 -SS_lm[13] Net - - - - 1cpu0.regs.SS[13] FD1P3AX D In 0.000 15.999 -========================================================================================================Path information for path number 5:Requested Period: 13.639- Setup time: -0.089+ Clock delay at ending point: 0.000 (ideal)= Required time: 13.728- Propagation time: 15.999- Clock delay at starting point: 0.000 (ideal)= Slack (non-critical) : -2.271Number of logic level(s): 20Starting point: cpu0.regs.IX_pipe_77 / QEnding point: cpu0.regs.SU[13] / DThe start point is clocked by CC3_top|clk40_i [rising] on pin CKThe end point is clocked by CC3_top|clk40_i [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)--------------------------------------------------------------------------------------------------------cpu0.regs.IX_pipe_77 FD1P3AX Q Out 0.972 0.972 -left_1f_0[0] Net - - - - 1cpu0.regs.IX_10_0[0] ORCALUT4 C In 0.000 0.972 -cpu0.regs.IX_10_0[0] ORCALUT4 Z Out 1.017 1.989 -N_631 Net - - - - 1cpu0.regs.IX_10[0] ORCALUT4 B In 0.000 1.989 -cpu0.regs.IX_10[0] ORCALUT4 Z Out 1.153 3.141 -IX[0] Net - - - - 3cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 B In 0.000 3.141 -cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 Z Out 1.017 4.158 -ea_reg_3_am[0] Net - - - - 1cpu0.regs.ea.ea_reg_3[0] PFUMX BLUT In 0.000 4.158 -cpu0.regs.ea.ea_reg_3[0] PFUMX Z Out 0.422 4.580 -ea_reg[0] Net - - - - 5cpu0.regs.ea.un1_pc_0[0] ORCALUT4 A In 0.000 4.580 -cpu0.regs.ea.un1_pc_0[0] ORCALUT4 Z Out 1.089 5.669 -N_72 Net - - - - 2cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D C1 In 0.000 5.669 -cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D COUT Out 1.545 7.214 -eamem_addr_o_cry_0 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D CIN In 0.000 7.214 -cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D COUT Out 0.143 7.356 -eamem_addr_o_cry_2 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D CIN In 0.000 7.356 -cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D COUT Out 0.143 7.499 -eamem_addr_o_cry_4 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D CIN In 0.000 7.499 -cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D COUT Out 0.143 7.642 -eamem_addr_o_cry_6 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D CIN In 0.000 7.642 -cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D COUT Out 0.143 7.785 -eamem_addr_o_cry_8 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D CIN In 0.000 7.785 -cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D COUT Out 0.143 7.928 -eamem_addr_o_cry_10 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D CIN In 0.000 7.928 -cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D COUT Out 0.143 8.070 -eamem_addr_o_cry_12 Net - - - - 1cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D CIN In 0.000 8.070 -cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D S0 Out 1.725 9.796 -regs_o_eamem_addr[13] Net - - - - 4cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 D In 0.000 9.796 -cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 Z Out 1.017 10.812 -datamux_o_dest_6[13] Net - - - - 1cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 B In 0.000 10.812 -cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 Z Out 1.017 11.829 -datamux_o_dest_am[13] Net - - - - 1cpu0.regs.ea.datamux_o_dest[13] PFUMX BLUT In 0.000 11.829 -cpu0.regs.ea.datamux_o_dest[13] PFUMX Z Out 0.286 12.115 -datamux_o_dest[13] Net - - - - 2cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 B In 0.000 12.115 -cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 Z Out 1.233 13.348 -left_1[13] Net - - - - 6cpu0.regs.SU_16_0[13] ORCALUT4 B In 0.000 13.348 -cpu0.regs.SU_16_0[13] ORCALUT4 Z Out 1.017 14.365 -N_294 Net - - - - 1cpu0.regs.SU_16[13] ORCALUT4 A In 0.000 14.365 -cpu0.regs.SU_16[13] ORCALUT4 Z Out 1.017 15.382 -SU_16[13] Net - - - - 1cpu0.regs.SU_lm_0[13] ORCALUT4 A In 0.000 15.382 -cpu0.regs.SU_lm_0[13] ORCALUT4 Z Out 0.617 15.999 -SU_lm[13] Net - - - - 1cpu0.regs.SU[13] FD1P3AX D In 0.000 15.999 -========================================================================================================##### END OF TIMING REPORT #####]---------------------------------------Resource Usage ReportPart: lcmxo2_7000he-4Register bits: 637 of 6864 (9%)PIC Latch: 0I/O cells: 69Block Rams : 10 of 26 (38%)Details:BB: 8CCU2D: 181DP8KC: 10FD1P3AX: 580FD1P3DX: 8FD1S3AX: 37FD1S3IX: 2GSR: 1IB: 1INV: 3L6MUX21: 20OB: 60OFS1P3DX: 9OFS1P3IX: 1ORCALUT4: 2122PFUMX: 255PUR: 1VHI: 14VLO: 20Mapper successful!At Mapper Exit (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:21s; Memory used current: 61MB peak: 241MB)Process took 0h:00m:21s realtime, 0h:00m:21s cputime# Wed Jul 02 14:52:48 2014###########################################################]