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[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809.srr] - Rev 4
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#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013#install: /usr/local/diamond/2.2_x64/synpbase#OS: Linux#Hostname: node01.pacito.sys#Implementation: P6809$ Start of Compile#Sun Dec 29 07:16:27 2013Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013@N|Running in 64-bit modeCopyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.@N:: Running Verilog Compiler in System Verilog mode@N:: Running Verilog Compiler in Multiple File Compilation Unit mode@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"Verilog syntax check successful!Selecting top level module CC3_top@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":13:7:13:11|Synthesizing module alu16@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":493:0:493:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":213:0:213:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":108:7:108:15|Synthesizing module decode_op@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":236:7:236:15|Synthesizing module decode_ea@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":262:7:262:16|Synthesizing module decode_alu@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":334:7:334:20|Synthesizing module test_condition@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":390:6:390:13|Ignoring system task $display@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":946:0:946:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_pull_reg_write -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_pp_active_reg[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_postbyte0[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_new_pc[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register bit k_mem_dest[0] is always 1, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register bit k_mem_dest[1] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register bit next_mem_state[1] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register bit next_mem_state[2] is always 0, optimizing ...@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Pruning register bits 2 to 1 of next_mem_state[5:0]@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":10:7:10:13|Synthesizing module CC3_top@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":31:14:31:21|No assignment to clk_div2@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|No assignment to wire cpu1_addr_o@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:40:37:51|No assignment to wire cpu1_data_in@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|No assignment to wire cpu1_data_out@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:23:38:29|No assignment to wire cpu1_we@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:32:38:38|No assignment to wire cpu1_oe@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Pruning register bits 5 to 2 of next_push_state[5:0]@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":338:18:338:20|Input port bits 7 to 4 of CCR[7:0] are unused@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":264:18:264:26|Input port bits 5 to 4 of postbyte0[7:0] are unused@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":237:18:237:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused@ENDProcess took 0h:00m:01s realtime, 0h:00m:01s cputime# Sun Dec 29 07:16:28 2013###########################################################]Premap ReportSynopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.Product Version G-2012.09L-SP1Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)@L: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_scck.rptPrinting clock summary report in "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_scck.rpt" file@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabledDesign Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 111MB)Clock Summary**************Start Requested Requested Clock ClockClock Frequency Period Type Group----------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Autoconstr_clkgroup_0======================================================================================================================@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 1 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.syn_allowed_resources : blockrams=26 set on top level netlist CC3_topFinished Pre Mapping Phase.Pre-mapping successful!At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 135MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputime# Sun Dec 29 07:16:30 2013###########################################################]Map & Optimize ReportSynopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.Product Version G-2012.09L-SP1Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabledDesign Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)Available hyper_sources - for debug and ip modelsNone Found@N: MT206 |Auto Constrain mode is enabledFinished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Found counter in view:work.MC6809_cpu(verilog) inst k_cpu_addr[15:0]@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Found counter in view:work.regblock(verilog) inst PC[15:0]@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_clear_e in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_set_e in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Removing sequential instance regs.fflag in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Removing sequential instance regs.intff in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Removing sequential instance regs.eflag in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputsFinished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 161MB)@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputsFinished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 156MB peak: 163MB)Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 163MB)@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":106:2:106:6|Pipelining module un1_ea_reg[15:0]@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register k_ind_ea[7:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Register DP[7:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":376:0:376:5|Register regq16[15:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register k_new_pc[15:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":376:0:376:5|Register regq8[7:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Register vff pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Register zff pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Register nff pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Register hflag pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register k_memhi[7:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":376:0:376:5|Register reg_z_in pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":376:0:376:5|Register reg_n_in pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register k_ealo[7:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register k_eahi[7:0] pushed in.@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":180:19:180:32|Pipelining module daa_lnm9@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":376:0:376:5|Register regq16[15:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":376:0:376:5|Register regq8[7:0] pushed in.@N: MF169 :|Register NoName pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register k_memlo[7:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Register DP[7:0] pushed in.Starting Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 163MB)Finished Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 157MB peak: 163MB)Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 156MB peak: 163MB)Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 155MB peak: 163MB)Finished technology mapping (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 231MB peak: 234MB)Pass CPU time Worst Slack Luts / Registers------------------------------------------------------------Pass CPU time Worst Slack Luts / Registers------------------------------------------------------------1 0h:00m:14s -7.90ns 1868 / 5452 0h:00m:14s -7.58ns 1868 / 5453 0h:00m:14s -7.58ns 1869 / 545------------------------------------------------------------@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[3]" with 7 loads replicated 1 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[2]" with 6 loads replicated 1 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[1]" with 6 loads replicated 1 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[4]" with 5 loads replicated 1 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[3]" with 53 loads replicated 3 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[0]" with 51 loads replicated 2 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[7]" with 45 loads replicated 2 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[6]" with 31 loads replicated 2 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[2]" with 57 loads replicated 3 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[4]" with 26 loads replicated 2 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[5]" with 26 loads replicated 2 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[1]" with 44 loads replicated 2 times to improve timingTiming driven replication reportAdded 22 Registers via timing driven replicationAdded 3 LUTs via timing driven replication@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[6]" with 6 loads replicated 1 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[7]" with 6 loads replicated 1 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[5]" with 7 loads replicated 1 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[0]" with 9 loads replicated 1 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_p2_valid" with 23 loads replicated 1 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_postbyte0[7]" with 19 loads replicated 1 times to improve timingAdded 6 Registers via timing driven replicationAdded 3 LUTs via timing driven replication@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_postbyte0[0]" with 17 loads replicated 1 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_postbyte0[6]" with 14 loads replicated 1 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_postbyte0[3]" with 14 loads replicated 1 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_postbyte0[2]" with 13 loads replicated 1 times to improve timing@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_p3_valid" with 12 loads replicated 1 times to improve timingAdded 5 Registers via timing driven replicationAdded 1 LUTs via timing driven replicationPass CPU time Worst Slack Luts / Registers------------------------------------------------------------1 0h:00m:16s -5.90ns 1913 / 5782 0h:00m:16s -5.90ns 1914 / 578------------------------------------------------------------Pass CPU time Worst Slack Luts / Registers------------------------------------------------------------1 0h:00m:16s -5.90ns 1917 / 578------------------------------------------------------------Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 169MB peak: 234MB)@N: FX164 |The option to pack flops in the IOB has not been specifiedFinished restoring hierarchy (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 171MB peak: 234MB)#### START OF CLOCK OPTIMIZATION REPORT #####[1 non-gated/non-generated clock tree(s) driving 582 clock pin(s) of sequential element(s)0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)292 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks=========================== Non-Gated/Non-Generated Clocks ============================Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance---------------------------------------------------------------------------------------@K:CKID0001 clk40_i port 582 cpu_clk============================================================================================ Gated/Generated Clocks =====************** None **************----------------------------------==================================##### END OF CLOCK OPTIMIZATION REPORT ######]Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809.srmFinished Writing Netlist Databases (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 173MB peak: 234MB)Writing EDIF Netlist and constraint filesG-2012.09L-SP1@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pFFinished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 177MB peak: 234MB)@W: MT420 |Found inferred clock CC3_top|clk40_i with period 18.92ns. Please declare a user-defined clock on object "p:clk40_i"##### START OF TIMING REPORT #####[# Timing Report written on Sun Dec 29 07:16:49 2013#Top view: CC3_topRequested Frequency: 52.8 MHzWire load mode: topPaths requested: 5Constraint File(s):@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.Performance Summary*******************Worst slack in design: -3.066Requested Estimated Requested Estimated Clock ClockStarting Clock Frequency Frequency Period Period Slack Type Group-------------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i 52.8 MHz 45.5 MHz 18.924 21.989 -3.066 inferred Autoconstr_clkgroup_0=========================================================================================================================Clock Relationships*******************Clocks | rise to rise | fall to fall | rise to fall | fall to rise-------------------------------------------------------------------------------------------------------------------------Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack-------------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i CC3_top|clk40_i | 18.924 -3.066 | No paths - | No paths - | No paths -=========================================================================================================================Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.Interface Information*********************No IO constraint found====================================Detailed Report for Clock: CC3_top|clk40_i====================================Starting Points with Worst Slack********************************Starting ArrivalInstance Reference Type Pin Net Time SlackClock---------------------------------------------------------------------------------------------------------cpu0.k_opcode_fast[0] CC3_top|clk40_i FD1P3AX Q k_opcode_fast[0] 1.188 -3.066cpu0.k_opcode_3_rep1 CC3_top|clk40_i FD1P3AX Q k_opcode_3_rep1 1.180 -3.058cpu0.k_opcode_2_rep1 CC3_top|clk40_i FD1P3AX Q k_opcode_2_rep1 1.148 -3.026cpu0.k_opcode_fast[7] CC3_top|clk40_i FD1P3AX Q k_opcode_fast[7] 1.204 -2.772cpu0.k_opcode_fast[1] CC3_top|clk40_i FD1P3AX Q k_opcode_fast[1] 1.188 -2.756cpu0.k_opcode_fast[3] CC3_top|clk40_i FD1P3AX Q k_opcode_fast[3] 1.188 -2.756cpu0.k_opcode_fast[5] CC3_top|clk40_i FD1P3AX Q k_opcode_fast[5] 1.148 -2.716cpu0.k_opcode_fast[6] CC3_top|clk40_i FD1P3AX Q k_opcode_fast[6] 1.148 -2.716cpu0.k_opcode_fast[2] CC3_top|clk40_i FD1P3AX Q k_opcode_fast[2] 1.108 -2.675cpu0.k_opcode_2_rep2 CC3_top|clk40_i FD1P3AX Q k_opcode_2_rep2 1.244 -2.575=========================================================================================================Ending Points with Worst Slack******************************Starting RequiredInstance Reference Type Pin Net Time SlackClock--------------------------------------------------------------------------------------------------cpu0.alu.regq16_pipe CC3_top|clk40_i FD1P3AX D N_712 19.012 -3.066cpu0.alu.regq16_pipe_11 CC3_top|clk40_i FD1P3AX D N_711 19.012 -2.923cpu0.alu.regq16_pipe_22 CC3_top|clk40_i FD1P3AX D N_710 19.012 -2.923cpu0.alu.regq16_pipe_33 CC3_top|clk40_i FD1P3AX D N_709 19.012 -2.780cpu0.alu.regq16_pipe_44 CC3_top|clk40_i FD1P3AX D N_708 19.012 -2.780cpu0.alu.regq16_pipe_55 CC3_top|clk40_i FD1P3AX D N_707 19.012 -2.638cpu0.alu.regq16_pipe_66 CC3_top|clk40_i FD1P3AX D N_706 19.012 -2.638cpu0.alu.regq16_pipe_97 CC3_top|clk40_i FD1P3AX D N_703 19.386 -2.592cpu0.regs.cff CC3_top|clk40_i FD1P3AX D N_27_i 19.012 -2.567cpu0.alu.regq16_pipe_88 CC3_top|clk40_i FD1P3AX D N_704 19.012 -2.567==================================================================================================Worst Path Information***********************Path information for path number 1:Requested Period: 18.924- Setup time: -0.089+ Clock delay at ending point: 0.000 (ideal)= Required time: 19.012- Propagation time: 22.078- Clock delay at starting point: 0.000 (ideal)= Slack (critical) : -3.066Number of logic level(s): 21Starting point: cpu0.k_opcode_fast[0] / QEnding point: cpu0.alu.regq16_pipe / DThe start point is clocked by CC3_top|clk40_i [rising] on pin CKThe end point is clocked by CC3_top|clk40_i [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)----------------------------------------------------------------------------------------------------------------------cpu0.k_opcode_fast[0] FD1P3AX Q Out 1.188 1.188 -k_opcode_fast[0] Net - - - - 6cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 C In 0.000 1.188 -cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 Z Out 1.017 2.205 -N_83 Net - - - - 1cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 A In 0.000 2.205 -cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 Z Out 1.017 3.221 -un1_dest_reg_2_sqmuxa_1_1_0_2_x0 Net - - - - 1cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 A In 0.000 3.221 -cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 Z Out 1.233 4.454 -un1_dest_reg_2_sqmuxa_1_1_0_2 Net - - - - 6cpu0.alu.datamux_m2 ORCALUT4 D In 0.000 4.454 -cpu0.alu.datamux_m2 ORCALUT4 Z Out 1.089 5.543 -datamux_m2 Net - - - - 2cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 A In 0.000 5.543 -cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 Z Out 1.017 6.560 -datamux_o_alu_in_left_path_data_a0_0_sx[0] Net - - - - 1cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 A In 0.000 6.560 -cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 Z Out 1.341 7.901 -datamux_o_alu_in_left_path_data_a1_0[0] Net - - - - 24cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 A In 0.000 7.901 -cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 Z Out 1.089 8.989 -datamux_o_alu_in_left_path_data_a1_0_0[0] Net - - - - 2cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 C In 0.000 8.989 -cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 Z Out 1.017 10.006 -datamux_o_alu_in_left_path_data_0_sx[0] Net - - - - 1cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 B In 0.000 10.006 -cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 Z Out 1.317 11.323 -datamux_o_alu_in_left_path_data[0] Net - - - - 18cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D C1 In 0.000 11.323 -cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D COUT Out 1.544 12.867 -mul16_w_madd_0_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D CIN In 0.000 12.867 -cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D S0 Out 1.621 14.489 -mul16_w_madd_0[2] Net - - - - 2cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D C1 In 0.000 14.489 -cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D COUT Out 1.544 16.033 -mul16_w_madd_4_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D CIN In 0.000 16.033 -cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D S1 Out 1.621 17.654 -mul16_w_madd Net - - - - 2cpu0.alu.mul16_w_madd_cry_0_0 CCU2D A1 In 0.000 17.654 -cpu0.alu.mul16_w_madd_cry_0_0 CCU2D COUT Out 1.544 19.198 -mul16_w_madd_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_cry_1_0 CCU2D CIN In 0.000 19.198 -cpu0.alu.mul16_w_madd_cry_1_0 CCU2D COUT Out 0.143 19.341 -mul16_w_madd_cry_2 Net - - - - 1cpu0.alu.mul16_w_madd_cry_3_0 CCU2D CIN In 0.000 19.341 -cpu0.alu.mul16_w_madd_cry_3_0 CCU2D COUT Out 0.143 19.484 -mul16_w_madd_cry_4 Net - - - - 1cpu0.alu.mul16_w_madd_cry_5_0 CCU2D CIN In 0.000 19.484 -cpu0.alu.mul16_w_madd_cry_5_0 CCU2D COUT Out 0.143 19.627 -mul16_w_madd_cry_6 Net - - - - 1cpu0.alu.mul16_w_madd_cry_7_0 CCU2D CIN In 0.000 19.627 -cpu0.alu.mul16_w_madd_cry_7_0 CCU2D COUT Out 0.143 19.770 -mul16_w_madd_cry_8 Net - - - - 1cpu0.alu.mul16_w_madd_cry_9_0 CCU2D CIN In 0.000 19.770 -cpu0.alu.mul16_w_madd_cry_9_0 CCU2D COUT Out 0.143 19.913 -mul16_w_madd_cry_10 Net - - - - 1cpu0.alu.mul16_w_madd_s_11_0 CCU2D CIN In 0.000 19.913 -cpu0.alu.mul16_w_madd_s_11_0 CCU2D S0 Out 1.549 21.462 -mul16_w[15] Net - - - - 1cpu0.alu.regq16_pipe_RNO ORCALUT4 C In 0.000 21.462 -cpu0.alu.regq16_pipe_RNO ORCALUT4 Z Out 0.617 22.078 -N_712 Net - - - - 1cpu0.alu.regq16_pipe FD1P3AX D In 0.000 22.078 -======================================================================================================================Path information for path number 2:Requested Period: 18.924- Setup time: -0.089+ Clock delay at ending point: 0.000 (ideal)= Required time: 19.012- Propagation time: 22.070- Clock delay at starting point: 0.000 (ideal)= Slack (non-critical) : -3.058Number of logic level(s): 21Starting point: cpu0.k_opcode_3_rep1 / QEnding point: cpu0.alu.regq16_pipe / DThe start point is clocked by CC3_top|clk40_i [rising] on pin CKThe end point is clocked by CC3_top|clk40_i [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)----------------------------------------------------------------------------------------------------------------------cpu0.k_opcode_3_rep1 FD1P3AX Q Out 1.180 1.180 -k_opcode_3_rep1 Net - - - - 5cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 B In 0.000 1.180 -cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 Z Out 1.017 2.197 -N_83 Net - - - - 1cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 A In 0.000 2.197 -cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 Z Out 1.017 3.213 -un1_dest_reg_2_sqmuxa_1_1_0_2_x0 Net - - - - 1cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 A In 0.000 3.213 -cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 Z Out 1.233 4.446 -un1_dest_reg_2_sqmuxa_1_1_0_2 Net - - - - 6cpu0.alu.datamux_m2 ORCALUT4 D In 0.000 4.446 -cpu0.alu.datamux_m2 ORCALUT4 Z Out 1.089 5.535 -datamux_m2 Net - - - - 2cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 A In 0.000 5.535 -cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 Z Out 1.017 6.552 -datamux_o_alu_in_left_path_data_a0_0_sx[0] Net - - - - 1cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 A In 0.000 6.552 -cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 Z Out 1.341 7.893 -datamux_o_alu_in_left_path_data_a1_0[0] Net - - - - 24cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 A In 0.000 7.893 -cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 Z Out 1.089 8.981 -datamux_o_alu_in_left_path_data_a1_0_0[0] Net - - - - 2cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 C In 0.000 8.981 -cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 Z Out 1.017 9.998 -datamux_o_alu_in_left_path_data_0_sx[0] Net - - - - 1cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 B In 0.000 9.998 -cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 Z Out 1.317 11.315 -datamux_o_alu_in_left_path_data[0] Net - - - - 18cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D C1 In 0.000 11.315 -cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D COUT Out 1.544 12.860 -mul16_w_madd_0_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D CIN In 0.000 12.860 -cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D S0 Out 1.621 14.480 -mul16_w_madd_0[2] Net - - - - 2cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D C1 In 0.000 14.480 -cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D COUT Out 1.544 16.025 -mul16_w_madd_4_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D CIN In 0.000 16.025 -cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D S1 Out 1.621 17.646 -mul16_w_madd Net - - - - 2cpu0.alu.mul16_w_madd_cry_0_0 CCU2D A1 In 0.000 17.646 -cpu0.alu.mul16_w_madd_cry_0_0 CCU2D COUT Out 1.544 19.191 -mul16_w_madd_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_cry_1_0 CCU2D CIN In 0.000 19.191 -cpu0.alu.mul16_w_madd_cry_1_0 CCU2D COUT Out 0.143 19.333 -mul16_w_madd_cry_2 Net - - - - 1cpu0.alu.mul16_w_madd_cry_3_0 CCU2D CIN In 0.000 19.333 -cpu0.alu.mul16_w_madd_cry_3_0 CCU2D COUT Out 0.143 19.476 -mul16_w_madd_cry_4 Net - - - - 1cpu0.alu.mul16_w_madd_cry_5_0 CCU2D CIN In 0.000 19.476 -cpu0.alu.mul16_w_madd_cry_5_0 CCU2D COUT Out 0.143 19.619 -mul16_w_madd_cry_6 Net - - - - 1cpu0.alu.mul16_w_madd_cry_7_0 CCU2D CIN In 0.000 19.619 -cpu0.alu.mul16_w_madd_cry_7_0 CCU2D COUT Out 0.143 19.762 -mul16_w_madd_cry_8 Net - - - - 1cpu0.alu.mul16_w_madd_cry_9_0 CCU2D CIN In 0.000 19.762 -cpu0.alu.mul16_w_madd_cry_9_0 CCU2D COUT Out 0.143 19.904 -mul16_w_madd_cry_10 Net - - - - 1cpu0.alu.mul16_w_madd_s_11_0 CCU2D CIN In 0.000 19.904 -cpu0.alu.mul16_w_madd_s_11_0 CCU2D S0 Out 1.549 21.453 -mul16_w[15] Net - - - - 1cpu0.alu.regq16_pipe_RNO ORCALUT4 C In 0.000 21.453 -cpu0.alu.regq16_pipe_RNO ORCALUT4 Z Out 0.617 22.070 -N_712 Net - - - - 1cpu0.alu.regq16_pipe FD1P3AX D In 0.000 22.070 -======================================================================================================================Path information for path number 3:Requested Period: 18.924- Setup time: -0.089+ Clock delay at ending point: 0.000 (ideal)= Required time: 19.012- Propagation time: 22.038- Clock delay at starting point: 0.000 (ideal)= Slack (non-critical) : -3.026Number of logic level(s): 21Starting point: cpu0.k_opcode_2_rep1 / QEnding point: cpu0.alu.regq16_pipe / DThe start point is clocked by CC3_top|clk40_i [rising] on pin CKThe end point is clocked by CC3_top|clk40_i [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)----------------------------------------------------------------------------------------------------------------------cpu0.k_opcode_2_rep1 FD1P3AX Q Out 1.148 1.148 -k_opcode_2_rep1 Net - - - - 4cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 A In 0.000 1.148 -cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 Z Out 1.017 2.165 -N_83 Net - - - - 1cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 A In 0.000 2.165 -cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 Z Out 1.017 3.181 -un1_dest_reg_2_sqmuxa_1_1_0_2_x0 Net - - - - 1cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 A In 0.000 3.181 -cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 Z Out 1.233 4.414 -un1_dest_reg_2_sqmuxa_1_1_0_2 Net - - - - 6cpu0.alu.datamux_m2 ORCALUT4 D In 0.000 4.414 -cpu0.alu.datamux_m2 ORCALUT4 Z Out 1.089 5.503 -datamux_m2 Net - - - - 2cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 A In 0.000 5.503 -cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 Z Out 1.017 6.520 -datamux_o_alu_in_left_path_data_a0_0_sx[0] Net - - - - 1cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 A In 0.000 6.520 -cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 Z Out 1.341 7.861 -datamux_o_alu_in_left_path_data_a1_0[0] Net - - - - 24cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 A In 0.000 7.861 -cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 Z Out 1.089 8.949 -datamux_o_alu_in_left_path_data_a1_0_0[0] Net - - - - 2cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 C In 0.000 8.949 -cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 Z Out 1.017 9.966 -datamux_o_alu_in_left_path_data_0_sx[0] Net - - - - 1cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 B In 0.000 9.966 -cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 Z Out 1.317 11.283 -datamux_o_alu_in_left_path_data[0] Net - - - - 18cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D C1 In 0.000 11.283 -cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D COUT Out 1.544 12.828 -mul16_w_madd_0_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D CIN In 0.000 12.828 -cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D S0 Out 1.621 14.448 -mul16_w_madd_0[2] Net - - - - 2cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D C1 In 0.000 14.448 -cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D COUT Out 1.544 15.993 -mul16_w_madd_4_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D CIN In 0.000 15.993 -cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D S1 Out 1.621 17.614 -mul16_w_madd Net - - - - 2cpu0.alu.mul16_w_madd_cry_0_0 CCU2D A1 In 0.000 17.614 -cpu0.alu.mul16_w_madd_cry_0_0 CCU2D COUT Out 1.544 19.159 -mul16_w_madd_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_cry_1_0 CCU2D CIN In 0.000 19.159 -cpu0.alu.mul16_w_madd_cry_1_0 CCU2D COUT Out 0.143 19.301 -mul16_w_madd_cry_2 Net - - - - 1cpu0.alu.mul16_w_madd_cry_3_0 CCU2D CIN In 0.000 19.301 -cpu0.alu.mul16_w_madd_cry_3_0 CCU2D COUT Out 0.143 19.444 -mul16_w_madd_cry_4 Net - - - - 1cpu0.alu.mul16_w_madd_cry_5_0 CCU2D CIN In 0.000 19.444 -cpu0.alu.mul16_w_madd_cry_5_0 CCU2D COUT Out 0.143 19.587 -mul16_w_madd_cry_6 Net - - - - 1cpu0.alu.mul16_w_madd_cry_7_0 CCU2D CIN In 0.000 19.587 -cpu0.alu.mul16_w_madd_cry_7_0 CCU2D COUT Out 0.143 19.730 -mul16_w_madd_cry_8 Net - - - - 1cpu0.alu.mul16_w_madd_cry_9_0 CCU2D CIN In 0.000 19.730 -cpu0.alu.mul16_w_madd_cry_9_0 CCU2D COUT Out 0.143 19.872 -mul16_w_madd_cry_10 Net - - - - 1cpu0.alu.mul16_w_madd_s_11_0 CCU2D CIN In 0.000 19.872 -cpu0.alu.mul16_w_madd_s_11_0 CCU2D S0 Out 1.549 21.422 -mul16_w[15] Net - - - - 1cpu0.alu.regq16_pipe_RNO ORCALUT4 C In 0.000 21.422 -cpu0.alu.regq16_pipe_RNO ORCALUT4 Z Out 0.617 22.038 -N_712 Net - - - - 1cpu0.alu.regq16_pipe FD1P3AX D In 0.000 22.038 -======================================================================================================================Path information for path number 4:Requested Period: 18.924- Setup time: -0.089+ Clock delay at ending point: 0.000 (ideal)= Required time: 19.012- Propagation time: 22.006- Clock delay at starting point: 0.000 (ideal)= Slack (non-critical) : -2.994Number of logic level(s): 21Starting point: cpu0.k_opcode_fast[0] / QEnding point: cpu0.alu.regq16_pipe / DThe start point is clocked by CC3_top|clk40_i [rising] on pin CKThe end point is clocked by CC3_top|clk40_i [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)----------------------------------------------------------------------------------------------------------------------cpu0.k_opcode_fast[0] FD1P3AX Q Out 1.188 1.188 -k_opcode_fast[0] Net - - - - 6cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 C In 0.000 1.188 -cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 Z Out 1.017 2.205 -N_83 Net - - - - 1cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 A In 0.000 2.205 -cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 Z Out 1.017 3.221 -un1_dest_reg_2_sqmuxa_1_1_0_2_x0 Net - - - - 1cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 A In 0.000 3.221 -cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 Z Out 1.233 4.454 -un1_dest_reg_2_sqmuxa_1_1_0_2 Net - - - - 6cpu0.alu.datamux_m2 ORCALUT4 D In 0.000 4.454 -cpu0.alu.datamux_m2 ORCALUT4 Z Out 1.089 5.543 -datamux_m2 Net - - - - 2cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 A In 0.000 5.543 -cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 Z Out 1.017 6.560 -datamux_o_alu_in_left_path_data_a0_0_sx[0] Net - - - - 1cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 A In 0.000 6.560 -cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 Z Out 1.341 7.901 -datamux_o_alu_in_left_path_data_a1_0[0] Net - - - - 24cpu0.alu.datamux_o_alu_in_left_path_data_0_1_1[0] ORCALUT4 A In 0.000 7.901 -cpu0.alu.datamux_o_alu_in_left_path_data_0_1_1[0] ORCALUT4 Z Out 1.017 8.917 -datamux_o_alu_in_left_path_data_0_1_1[0] Net - - - - 1cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 B In 0.000 8.917 -cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 Z Out 1.017 9.934 -datamux_o_alu_in_left_path_data_0_sx[0] Net - - - - 1cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 B In 0.000 9.934 -cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 Z Out 1.317 11.251 -datamux_o_alu_in_left_path_data[0] Net - - - - 18cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D C1 In 0.000 11.251 -cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D COUT Out 1.544 12.796 -mul16_w_madd_0_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D CIN In 0.000 12.796 -cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D S0 Out 1.621 14.416 -mul16_w_madd_0[2] Net - - - - 2cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D C1 In 0.000 14.416 -cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D COUT Out 1.544 15.961 -mul16_w_madd_4_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D CIN In 0.000 15.961 -cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D S1 Out 1.621 17.582 -mul16_w_madd Net - - - - 2cpu0.alu.mul16_w_madd_cry_0_0 CCU2D A1 In 0.000 17.582 -cpu0.alu.mul16_w_madd_cry_0_0 CCU2D COUT Out 1.544 19.127 -mul16_w_madd_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_cry_1_0 CCU2D CIN In 0.000 19.127 -cpu0.alu.mul16_w_madd_cry_1_0 CCU2D COUT Out 0.143 19.269 -mul16_w_madd_cry_2 Net - - - - 1cpu0.alu.mul16_w_madd_cry_3_0 CCU2D CIN In 0.000 19.269 -cpu0.alu.mul16_w_madd_cry_3_0 CCU2D COUT Out 0.143 19.412 -mul16_w_madd_cry_4 Net - - - - 1cpu0.alu.mul16_w_madd_cry_5_0 CCU2D CIN In 0.000 19.412 -cpu0.alu.mul16_w_madd_cry_5_0 CCU2D COUT Out 0.143 19.555 -mul16_w_madd_cry_6 Net - - - - 1cpu0.alu.mul16_w_madd_cry_7_0 CCU2D CIN In 0.000 19.555 -cpu0.alu.mul16_w_madd_cry_7_0 CCU2D COUT Out 0.143 19.698 -mul16_w_madd_cry_8 Net - - - - 1cpu0.alu.mul16_w_madd_cry_9_0 CCU2D CIN In 0.000 19.698 -cpu0.alu.mul16_w_madd_cry_9_0 CCU2D COUT Out 0.143 19.840 -mul16_w_madd_cry_10 Net - - - - 1cpu0.alu.mul16_w_madd_s_11_0 CCU2D CIN In 0.000 19.840 -cpu0.alu.mul16_w_madd_s_11_0 CCU2D S0 Out 1.549 21.390 -mul16_w[15] Net - - - - 1cpu0.alu.regq16_pipe_RNO ORCALUT4 C In 0.000 21.390 -cpu0.alu.regq16_pipe_RNO ORCALUT4 Z Out 0.617 22.006 -N_712 Net - - - - 1cpu0.alu.regq16_pipe FD1P3AX D In 0.000 22.006 -======================================================================================================================Path information for path number 5:Requested Period: 18.924- Setup time: -0.089+ Clock delay at ending point: 0.000 (ideal)= Required time: 19.012- Propagation time: 22.006- Clock delay at starting point: 0.000 (ideal)= Slack (non-critical) : -2.994Number of logic level(s): 21Starting point: cpu0.k_opcode_fast[0] / QEnding point: cpu0.alu.regq16_pipe / DThe start point is clocked by CC3_top|clk40_i [rising] on pin CKThe end point is clocked by CC3_top|clk40_i [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)----------------------------------------------------------------------------------------------------------------------cpu0.k_opcode_fast[0] FD1P3AX Q Out 1.188 1.188 -k_opcode_fast[0] Net - - - - 6cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 C In 0.000 1.188 -cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 Z Out 1.017 2.205 -N_83 Net - - - - 1cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 A In 0.000 2.205 -cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 Z Out 1.017 3.221 -un1_dest_reg_2_sqmuxa_1_1_0_2_x0 Net - - - - 1cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 A In 0.000 3.221 -cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 Z Out 1.233 4.454 -un1_dest_reg_2_sqmuxa_1_1_0_2 Net - - - - 6cpu0.alu.datamux_m2 ORCALUT4 D In 0.000 4.454 -cpu0.alu.datamux_m2 ORCALUT4 Z Out 1.089 5.543 -datamux_m2 Net - - - - 2cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 A In 0.000 5.543 -cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 Z Out 1.017 6.560 -datamux_o_alu_in_left_path_data_a0_0_sx[0] Net - - - - 1cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 A In 0.000 6.560 -cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 Z Out 1.341 7.901 -datamux_o_alu_in_left_path_data_a1_0[0] Net - - - - 24cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 A In 0.000 7.901 -cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 Z Out 1.089 8.989 -datamux_o_alu_in_left_path_data_a1_0_0[0] Net - - - - 2cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 C In 0.000 8.989 -cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 Z Out 1.017 10.006 -datamux_o_alu_in_left_path_data_0_sx[0] Net - - - - 1cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 B In 0.000 10.006 -cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 Z Out 1.317 11.323 -datamux_o_alu_in_left_path_data[0] Net - - - - 18cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D C1 In 0.000 11.323 -cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D COUT Out 1.544 12.867 -mul16_w_madd_0_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D CIN In 0.000 12.867 -cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D COUT Out 0.143 13.010 -mul16_w_madd_0_cry_2 Net - - - - 1cpu0.alu.mul16_w_madd_0_cry_3_0 CCU2D CIN In 0.000 13.010 -cpu0.alu.mul16_w_madd_0_cry_3_0 CCU2D COUT Out 0.143 13.153 -mul16_w_madd_0_cry_4 Net - - - - 1cpu0.alu.mul16_w_madd_0_cry_5_0 CCU2D CIN In 0.000 13.153 -cpu0.alu.mul16_w_madd_0_cry_5_0 CCU2D S0 Out 1.621 14.774 -mul16_w_madd_0[6] Net - - - - 2cpu0.alu.mul16_w_madd_5_cry_2_0 CCU2D B1 In 0.000 14.774 -cpu0.alu.mul16_w_madd_5_cry_2_0 CCU2D COUT Out 1.544 16.319 -mul16_w_madd_5_cry_2 Net - - - - 1cpu0.alu.mul16_w_madd_5_cry_3_0 CCU2D CIN In 0.000 16.319 -cpu0.alu.mul16_w_madd_5_cry_3_0 CCU2D S1 Out 1.549 17.868 -mul16_w_madd_5[8] Net - - - - 1cpu0.alu.mul16_w_madd_cry_3_0 CCU2D A1 In 0.000 17.868 -cpu0.alu.mul16_w_madd_cry_3_0 CCU2D COUT Out 1.544 19.412 -mul16_w_madd_cry_4 Net - - - - 1cpu0.alu.mul16_w_madd_cry_5_0 CCU2D CIN In 0.000 19.412 -cpu0.alu.mul16_w_madd_cry_5_0 CCU2D COUT Out 0.143 19.555 -mul16_w_madd_cry_6 Net - - - - 1cpu0.alu.mul16_w_madd_cry_7_0 CCU2D CIN In 0.000 19.555 -cpu0.alu.mul16_w_madd_cry_7_0 CCU2D COUT Out 0.143 19.698 -mul16_w_madd_cry_8 Net - - - - 1cpu0.alu.mul16_w_madd_cry_9_0 CCU2D CIN In 0.000 19.698 -cpu0.alu.mul16_w_madd_cry_9_0 CCU2D COUT Out 0.143 19.840 -mul16_w_madd_cry_10 Net - - - - 1cpu0.alu.mul16_w_madd_s_11_0 CCU2D CIN In 0.000 19.840 -cpu0.alu.mul16_w_madd_s_11_0 CCU2D S0 Out 1.549 21.390 -mul16_w[15] Net - - - - 1cpu0.alu.regq16_pipe_RNO ORCALUT4 C In 0.000 21.390 -cpu0.alu.regq16_pipe_RNO ORCALUT4 Z Out 0.617 22.006 -N_712 Net - - - - 1cpu0.alu.regq16_pipe FD1P3AX D In 0.000 22.006 -======================================================================================================================##### END OF TIMING REPORT #####]---------------------------------------Resource Usage ReportPart: lcmxo2_7000he-4Register bits: 578 of 6864 (8%)PIC Latch: 0I/O cells: 49Block Rams : 2 of 26 (7%)Details:CCU2D: 162DP8KC: 2FD1P3AX: 558FD1P3DX: 6FD1P3IX: 1FD1P3JX: 4FD1S3AX: 1GSR: 1IB: 1INV: 5L6MUX21: 10OB: 48OFS1P3DX: 8ORCALUT4: 1908PFUMX: 181PUR: 1VHI: 4VLO: 10Mapper successful!At Mapper Exit (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 45MB peak: 234MB)Process took 0h:00m:18s realtime, 0h:00m:18s cputime# Sun Dec 29 07:16:49 2013###########################################################]
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