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[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [automake.log] - Rev 5
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synpwrap -prj "P6809_P6809_synplify.tcl" -log "P6809_P6809.srf"*****************************************************************Warning: You are running on an unsupported platform'synplify_pro' only supports Red Hat Enterprise Linux 4.0 and abovecurrent platform: CentOS release 6.4 (Final)Kernel \r on an \m*****************************************************************Running in Lattice modeStarting: /usr/local/diamond/2.2_x64/synpbase/linux_a_64/mbin/synbatchInstall: /usr/local/diamond/2.2_x64/synpbaseDate: Tue Dec 31 08:52:23 2013Version: G-2012.09L-SP1Arguments: -product synplify_pro -batch P6809_P6809_synplify.tclProductType: synplify_prolog file: "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr"Running proj_1|P6809Running Compile on proj_1|P6809Running Compile Process on proj_1|P6809Running Compile Input on proj_1|P6809Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/synwork/P6809_P6809_compiler.srs to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srscompiler Completed with warningsReturn Code: 1Run Time:00h:00m:03sCopied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srfJob Compile Process completed on proj_1|P6809Running Premap on proj_1|P6809premap Completed with warningsReturn Code: 1Run Time:00h:00m:01sJob Compile completed on proj_1|P6809Running Map on proj_1|P6809Running Map & Optimize on proj_1|P6809fpga_mapper Completed with warningsReturn Code: 1Run Time:00h:00m:19sJob Map completed on proj_1|P6809Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srfJob Logic Synthesis completed on proj_1|P6809TCL script complete: "P6809_P6809_synplify.tcl"exit status=0Copyright (C) 1992-2013 Lattice Semiconductor Corporation. All rights reserved.Lattice Diamond Version 2.2.0.101Child process exit with 0.==contents of P6809_P6809.srf#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013#install: /usr/local/diamond/2.2_x64/synpbase#OS: Linux#Hostname: node01.pacito.sys#Implementation: P6809$ Start of Compile#Tue Dec 31 08:52:23 2013Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013@N|Running in 64-bit modeCopyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"Verilog syntax check successful!File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v changed - recompilingSelecting top level module CC3_top@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":13:7:13:11|Synthesizing module alu16@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":500:0:500:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":244:0:244:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":131:7:131:15|Synthesizing module decode_op@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":259:7:259:15|Synthesizing module decode_ea@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":285:7:285:16|Synthesizing module decode_alu@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":358:7:358:20|Synthesizing module test_condition@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":429:6:429:13|Ignoring system task $display@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":967:0:967:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_pp_active_reg[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Register bit k_mem_dest[0] is always 1, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Register bit k_mem_dest[1] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Register bit next_mem_state[1] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Register bit next_mem_state[2] is always 0, optimizing ...@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Pruning register bits 2 to 1 of next_mem_state[5:0]@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":10:7:10:13|Synthesizing module CC3_top@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":31:14:31:21|No assignment to clk_div2@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|No assignment to wire cpu1_addr_o@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:40:37:51|No assignment to wire cpu1_data_in@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|No assignment to wire cpu1_data_out@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:23:38:29|No assignment to wire cpu1_we@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:32:38:38|No assignment to wire cpu1_oe@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Pruning register bits 5 to 2 of next_push_state[5:0]@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":362:18:362:20|Input port bits 7 to 4 of CCR[7:0] are unused@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":287:18:287:26|Input port bits 5 to 4 of postbyte0[7:0] are unused@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":260:18:260:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused@ENDProcess took 0h:00m:01s realtime, 0h:00m:01s cputime# Tue Dec 31 08:52:25 2013###########################################################]Premap ReportSynopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.Product Version G-2012.09L-SP1Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)@L: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rptPrinting clock summary report in "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt" file@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabledDesign Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 111MB)Clock Summary**************Start Requested Requested Clock ClockClock Frequency Period Type Group--------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i 1.0 MHz 1000.000 inferred Inferred_clkgroup_0CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0====================================================================================================================@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 1 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.syn_allowed_resources : blockrams=26 set on top level netlist CC3_topFinished Pre Mapping Phase.Pre-mapping successful!At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 136MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputime# Tue Dec 31 08:52:27 2013###########################################################]Map & Optimize ReportSynopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.Product Version G-2012.09L-SP1Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabledDesign Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)Available hyper_sources - for debug and ip modelsNone FoundFinished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Found counter in view:work.regblock(verilog) inst PC[15:0]@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputsFinished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 156MB peak: 157MB)@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputsFinished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 160MB)Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 162MB)@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":24:22:24:42|Pipelining module result_size@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":380:0:380:5|Register regq8[7:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":380:0:380:5|Register regq16[15:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register hflag pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register intff pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":380:0:380:5|Register reg_z_in pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":380:0:380:5|Register reg_n_in pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register vff pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register cff pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Register k_memlo[7:0] pushed in.@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":228:2:228:3|Pipelining module un1_old_su_1[15:0]@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register SS[15:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register DP[7:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register ACCB[7:0] pushed in.@N: MF169 :|Register NoName pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register IX[15:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register IY[15:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register SU[15:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":380:0:380:5|Register regq16[15:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register zff pushed in.@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":264:2:264:5|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.k_new_pc_4[15:0] from cpu0.un1_regs_o_pc[15:0]Starting Early Timing Optimization (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 152MB peak: 162MB)Finished Early Timing Optimization (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 152MB peak: 162MB)Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 151MB peak: 162MB)Finished preparing to map (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 149MB peak: 162MB)Finished technology mapping (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 191MB peak: 228MB)Pass CPU time Worst Slack Luts / Registers------------------------------------------------------------Pass CPU time Worst Slack Luts / Registers------------------------------------------------------------------------------------------------------------------------Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 166MB peak: 228MB)@N: FX164 |The option to pack flops in the IOB has not been specifiedFinished restoring hierarchy (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 167MB peak: 228MB)#### START OF CLOCK OPTIMIZATION REPORT #####[1 non-gated/non-generated clock tree(s) driving 577 clock pin(s) of sequential element(s)0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)223 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks=========================== Non-Gated/Non-Generated Clocks ============================Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance---------------------------------------------------------------------------------------@K:CKID0001 clk40_i port 577 cpu_clk============================================================================================ Gated/Generated Clocks =====************** None **************----------------------------------==================================##### END OF CLOCK OPTIMIZATION REPORT ######]Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srmFinished Writing Netlist Databases (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 169MB peak: 228MB)Writing EDIF Netlist and constraint filesG-2012.09L-SP1@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pFFinished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 173MB peak: 228MB)@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"##### START OF TIMING REPORT #####[# Timing Report written on Tue Dec 31 08:52:45 2013#Top view: CC3_topRequested Frequency: 1.0 MHzWire load mode: topPaths requested: 5Constraint File(s):@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.Performance Summary*******************Worst slack in design: 971.433Requested Estimated Requested Estimated Clock ClockStarting Clock Frequency Frequency Period Period Slack Type Group------------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i 1.0 MHz 35.0 MHz 1000.000 28.567 971.433 inferred Inferred_clkgroup_0========================================================================================================================Clock Relationships*******************Clocks | rise to rise | fall to fall | rise to fall | fall to rise--------------------------------------------------------------------------------------------------------------------------Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack--------------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i CC3_top|clk40_i | 1000.000 971.434 | No paths - | No paths - | No paths -==========================================================================================================================Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.Interface Information*********************No IO constraint found====================================Detailed Report for Clock: CC3_top|clk40_i====================================Starting Points with Worst Slack********************************Starting ArrivalInstance Reference Type Pin Net Time SlackClock----------------------------------------------------------------------------------------------------cpu0.k_opcode[4] CC3_top|clk40_i FD1P3AX Q k_opcode[4] 1.333 971.433cpu0.k_opcode[5] CC3_top|clk40_i FD1P3AX Q k_opcode[5] 1.326 971.441cpu0.k_opcode[0] CC3_top|clk40_i FD1P3AX Q k_opcode[0] 1.358 971.513cpu0.k_opcode[3] CC3_top|clk40_i FD1P3AX Q k_opcode[3] 1.352 971.519cpu0.k_opcode[1] CC3_top|clk40_i FD1P3AX Q k_opcode[1] 1.344 971.527cpu0.k_opcode[7] CC3_top|clk40_i FD1P3AX Q k_opcode[7] 1.344 972.368cpu0.k_opcode[6] CC3_top|clk40_i FD1P3AX Q k_opcode[6] 1.336 972.416cpu0.k_opcode[2] CC3_top|clk40_i FD1P3AX Q k_opcode[2] 1.368 972.560cpu0.k_postbyte[5] CC3_top|clk40_i FD1P3AX Q k_postbyte[5] 1.276 973.285cpu0.k_postbyte[4] CC3_top|clk40_i FD1P3AX Q k_postbyte[4] 1.256 973.306====================================================================================================Ending Points with Worst Slack******************************Starting RequiredInstance Reference Type Pin Net Time SlackClock-----------------------------------------------------------------------------------------------------cpu0.alu.regq16_pipe_124 CC3_top|clk40_i FD1P3AX D N_911 1000.462 971.433cpu0.alu.regq16_pipe_28 CC3_top|clk40_i FD1P3AX D N_910_0 1000.462 971.648cpu0.alu.regq16_pipe_32 CC3_top|clk40_i FD1P3AX D N_909 1000.462 971.648cpu0.alu.regq16_pipe_38 CC3_top|clk40_i FD1P3AX D N_919 1000.462 971.951cpu0.alu.regq16_pipe_49 CC3_top|clk40_i FD1P3AX D N_918 1000.462 972.094cpu0.alu.regq16_pipe_60 CC3_top|clk40_i FD1P3AX D N_917 1000.462 972.094cpu0.alu.regq16_pipe_71 CC3_top|clk40_i FD1P3AX D N_916 1000.462 972.237cpu0.alu.regq16_pipe_82 CC3_top|clk40_i FD1P3AX D N_915 1000.462 972.237cpu0.alu.regq16_pipe_93 CC3_top|clk40_i FD1P3AX D N_914 1000.462 972.380cpu0.alu.regq16_pipe_104 CC3_top|clk40_i FD1P3AX D N_913 1000.462 972.380=====================================================================================================Worst Path Information***********************Path information for path number 1:Requested Period: 1000.000- Setup time: -0.462+ Clock delay at ending point: 0.000 (ideal)= Required time: 1000.462- Propagation time: 29.029- Clock delay at starting point: 0.000 (ideal)= Slack (critical) : 971.433Number of logic level(s): 25Starting point: cpu0.k_opcode[4] / QEnding point: cpu0.alu.regq16_pipe_124 / DThe start point is clocked by CC3_top|clk40_i [rising] on pin CKThe end point is clocked by CC3_top|clk40_i [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)-------------------------------------------------------------------------------------------------------------------------cpu0.k_opcode[4] FD1P3AX Q Out 1.333 1.333 -k_opcode[4] Net - - - - 38cpu0.dec_regs.state53_2_i_o2 ORCALUT4 A In 0.000 1.333 -cpu0.dec_regs.state53_2_i_o2 ORCALUT4 Z Out 1.193 2.526 -N_76 Net - - - - 4cpu0.dec_regs.un1_dest_reg53_2_0_a2 ORCALUT4 B In 0.000 2.526 -cpu0.dec_regs.un1_dest_reg53_2_0_a2 ORCALUT4 Z Out 1.089 3.615 -N_54_mux Net - - - - 2cpu0.dec_regs.un1_dest_reg53_2_0 ORCALUT4 D In 0.000 3.615 -cpu0.dec_regs.un1_dest_reg53_2_0 ORCALUT4 Z Out 1.089 4.704 -un1_dest_reg53_2 Net - - - - 2cpu0.dec_regs.un1_dest_reg44_1_2 ORCALUT4 C In 0.000 4.704 -cpu0.dec_regs.un1_dest_reg44_1_2 ORCALUT4 Z Out 1.153 5.857 -un1_dest_reg44_1_2 Net - - - - 3cpu0.dec_regs.un1_dest_reg44_1 ORCALUT4 B In 0.000 5.857 -cpu0.dec_regs.un1_dest_reg44_1 ORCALUT4 Z Out 1.089 6.945 -un1_dest_reg44_1 Net - - - - 2cpu0.dec_regs.path_left_addr_2_sqmuxa ORCALUT4 B In 0.000 6.945 -cpu0.dec_regs.path_left_addr_2_sqmuxa ORCALUT4 Z Out 1.233 8.178 -path_left_addr_2_sqmuxa Net - - - - 6cpu0.dec_regs.un1_dest_reg44_1_RNIU7BO ORCALUT4 A In 0.000 8.178 -cpu0.dec_regs.un1_dest_reg44_1_RNIU7BO ORCALUT4 Z Out 1.089 9.267 -N_519 Net - - - - 2cpu0.dec_regs.path_left_addr_bm[0] ORCALUT4 A In 0.000 9.267 -cpu0.dec_regs.path_left_addr_bm[0] ORCALUT4 Z Out 1.017 10.284 -path_left_addr_bm[0] Net - - - - 1cpu0.dec_regs.path_left_addr[0] PFUMX ALUT In 0.000 10.284 -cpu0.dec_regs.path_left_addr[0] PFUMX Z Out 0.350 10.634 -dec_o_left_path_addr[0] Net - - - - 3cpu0.regs.datamux_o_alu_in_left_path_addr_1_0[0] ORCALUT4 B In 0.000 10.634 -cpu0.regs.datamux_o_alu_in_left_path_addr_1_0[0] ORCALUT4 Z Out 1.017 11.651 -N_1062 Net - - - - 1cpu0.regs.datamux_o_alu_in_left_path_addr_1[0] ORCALUT4 A In 0.000 11.651 -cpu0.regs.datamux_o_alu_in_left_path_addr_1[0] ORCALUT4 Z Out 1.384 13.035 -datamux_o_alu_in_left_path_addr_1[0] Net - - - - 41cpu0.regs.datamux_o_alu_in_left_path_addr_1_RNIUM5T[1] ORCALUT4 A In 0.000 13.035 -cpu0.regs.datamux_o_alu_in_left_path_addr_1_RNIUM5T[1] ORCALUT4 Z Out 1.313 14.348 -N_873 Net - - - - 17cpu0.regs.path_left_data_bm[0] ORCALUT4 C In 0.000 14.348 -cpu0.regs.path_left_data_bm[0] ORCALUT4 Z Out 1.017 15.364 -path_left_data_bm[0] Net - - - - 1cpu0.regs.path_left_data[0] PFUMX ALUT In 0.000 15.364 -cpu0.regs.path_left_data[0] PFUMX Z Out 0.390 15.755 -regs_o_left_path_data[0] Net - - - - 4cpu0.alu.datamux_o_alu_in_left_path_data[0] ORCALUT4 A In 0.000 15.755 -cpu0.alu.datamux_o_alu_in_left_path_data[0] ORCALUT4 Z Out 1.387 17.142 -datamux_o_alu_in_left_path_data[0] Net - - - - 43cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D C1 In 0.000 17.142 -cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D COUT Out 1.544 18.686 -mul16_w_madd_0_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D CIN In 0.000 18.686 -cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D S0 Out 1.621 20.307 -mul16_w_madd_0[2] Net - - - - 2cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D C1 In 0.000 20.307 -cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D COUT Out 1.544 21.852 -mul16_w_madd_4_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D CIN In 0.000 21.852 -cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D S1 Out 1.621 23.473 -mul16_w_madd Net - - - - 2cpu0.alu.mul16_w_madd_cry_0_0 CCU2D A1 In 0.000 23.473 -cpu0.alu.mul16_w_madd_cry_0_0 CCU2D COUT Out 1.544 25.017 -mul16_w_madd_cry_0 Net - - - - 1cpu0.alu.mul16_w_madd_cry_1_0 CCU2D CIN In 0.000 25.017 -cpu0.alu.mul16_w_madd_cry_1_0 CCU2D COUT Out 0.143 25.160 -mul16_w_madd_cry_2 Net - - - - 1cpu0.alu.mul16_w_madd_cry_3_0 CCU2D CIN In 0.000 25.160 -cpu0.alu.mul16_w_madd_cry_3_0 CCU2D S0 Out 1.621 26.781 -mul16_w[7] Net - - - - 2cpu0.alu.q16_20[7] ORCALUT4 A In 0.000 26.781 -cpu0.alu.q16_20[7] ORCALUT4 Z Out 1.017 27.798 -N_847 Net - - - - 1cpu0.alu.q16_24_am[7] ORCALUT4 A In 0.000 27.798 -cpu0.alu.q16_24_am[7] ORCALUT4 Z Out 1.017 28.815 -q16_24_am[7] Net - - - - 1cpu0.alu.q16_24[7] PFUMX BLUT In 0.000 28.815 -cpu0.alu.q16_24[7] PFUMX Z Out 0.214 29.029 -N_911 Net - - - - 1cpu0.alu.regq16_pipe_124 FD1P3AX D In 0.000 29.029 -=========================================================================================================================##### END OF TIMING REPORT #####]---------------------------------------Resource Usage ReportPart: lcmxo2_7000he-4Register bits: 573 of 6864 (8%)PIC Latch: 0I/O cells: 49Block Rams : 2 of 26 (7%)Details:CCU2D: 162DP8KC: 2FD1P3AX: 552FD1P3DX: 6FD1P3IX: 2FD1P3JX: 4FD1S3AX: 1GSR: 1IB: 1INV: 11L6MUX21: 22OB: 48OFS1P3DX: 8ORCALUT4: 2177PFUMX: 315PUR: 1VHI: 4VLO: 10true: 6Mapper successful!At Mapper Exit (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 44MB peak: 228MB)Process took 0h:00m:18s realtime, 0h:00m:18s cputime# Tue Dec 31 08:52:45 2013###########################################################]Synthesis exit by 0.edif2ngd -l "MachXO2" -d LCMXO2-7000HE -path "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -path "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice" "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi" "P6809_P6809.ngo"edif2ngd: version Diamond (64-bit) 2.2.0.101Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...On or above line 291 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property is_pwr found - ignoring...On or above line 299 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 610 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 1405 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 1481 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 2852 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 6393 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 18874 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 33610 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 34028 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 38347 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 39078 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWriting the design to P6809_P6809.ngo...ngdbuild -a "MachXO2" -d LCMXO2-7000HE -p "/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data" -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice" "P6809_P6809.ngo" "P6809_P6809.ngd"ngdbuild: version Diamond (64-bit) 2.2.0.101Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Reading 'P6809_P6809.ngo' ...Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data/xo2clib.ngl'...Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/mg5g00/data/mg5glib.ngl'...Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/or5g00/data/orc5glib.ngl'...Running DRC...WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_s_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_s_15_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_s_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_s_15_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/un1_old_su_1_s_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/un1_old_su_1_s_15_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/un1_old_su_1_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/un1_old_su_1_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_s_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_s_15_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/PC_cry_0_COUT[14]' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/PC_lcry_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/PC_lcry_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_s_11_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_s_11_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_5_s_11_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_5_s_11_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_5_cry_2_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_5_cry_2_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_4_cry_9_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_4_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_4_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_3_cry_8_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_3_cry_1_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_3_cry_1_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_1_cry_8_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_1_cry_1_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_1_cry_1_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_2_cry_8_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_2_cry_1_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_2_cry_1_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_0_cry_7_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_0_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_0_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/neg16_w_s_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/neg16_w_s_15_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/neg16_w_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/neg16_w_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sbc8_w_cry_7_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sbc8_w_cry_7_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sbc8_w_cry_5_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sbc8_w_cry_5_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sbc8_w_cry_3_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sbc8_w_cry_3_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sbc8_w_cry_1_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sbc8_w_cry_1_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sbc8_w_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sbc16_w_cry_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sbc16_w_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sub16_w_cry_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sub16_w_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sub16_w_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_7_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_7_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_5_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_5_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_3_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_3_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_1_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_1_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/add16_w_cry_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/add16_w_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/add16_w_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_s_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_s_15_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_cry_13_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_cry_13_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_cry_11_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_cry_11_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_cry_9_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_cry_9_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_cry_7_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_cry_5_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_cry_5_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_cry_3_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_cry_3_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_cry_1_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_cry_1_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/adc16_w_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_7_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_7_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_5_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_5_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_3_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_3_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_1_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_1_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/k_new_pc_4_s_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/k_new_pc_4_s_15_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/k_new_pc_4_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/k_new_pc_4_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S1' has no loadWARNING - ngdbuild: DRC complete with 108 warningsDesign Results:3326 blocks expandedcomplete the first expansionWriting 'P6809_P6809.ngd' ...map -a "MachXO2" -p LCMXO2-7000HE -t TQFP144 -s 4 -oc Commercial "P6809_P6809.ngd" -o "P6809_P6809_map.ncd" -pr "P6809_P6809.prf" -mp "P6809_P6809.mrp" "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809.lpf" -c 0map: version Diamond (64-bit) 2.2.0.101Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Process the file: P6809_P6809.ngdPicdevice="LCMXO2-7000HE"Pictype="TQFP144"Picspeed=4Remove unused logicDo not produce over sized NCDs.Part used: LCMXO2-7000HETQFP144, Performance used: 4.Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.Package Status: Final Version 1.36Running general design DRC...Removing unused logic...Optimizing...7 CCU2 constant inputs absorbed.WARNING - map: Using local reset signal 'cpu0.cpu_reset_i_2_i' to infer global GSR net.WARNING - map: The reset of EBR 'bios/bios2k_0_1_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.WARNING - map: The reset of EBR 'bios/bios2k_0_0_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.Design Summary:Number of registers: 573PFU registers: 565PIO registers: 8Number of SLICEs: 1259 out of 3432 (37%)SLICEs(logic/ROM): 858 out of 858 (100%)SLICEs(logic/ROM/RAM): 401 out of 2574 (16%)As RAM: 0 out of 2574 (0%)As Logic/ROM: 401 out of 2574 (16%)Number of logic LUT4s: 2189Number of distributed RAM: 0 (0 LUT4s)Number of ripple logic: 162 (324 LUT4s)Number of shift registers: 0Total number of LUT4s: 2513Number of PIO sites used: 49 + 4(JTAG) out of 115 (46%)Number of block RAMs: 2 out of 26 (8%)Number of GSRs: 1 out of 1 (100%)EFB used : NoJTAG used : NoReadback used : NoOscillator used : NoStartup used : NoPOR : OnBandgap : OnNumber of Power Controller: 0 out of 1 (0%)Number of Dynamic Bank Controller (BCINRD): 0 out of 6 (0%)Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)Number of DCCA: 0 out of 8 (0%)Number of DCMA: 0 out of 2 (0%)Number of PLLs: 0 out of 2 (0%)Number of DQSDLLs: 0 out of 2 (0%)Number of CLKDIVC: 0 out of 4 (0%)Number of ECLKSYNCA: 0 out of 4 (0%)Number of ECLKBRIDGECS: 0 out of 2 (0%)Notes:-1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.Number of clocks: 1Net cpu_clkgen: 374 loads, 374 rising, 0 falling (Driver: PIO clk40_i )Number of Clock Enables: 27Net cpu_clk: 187 loads, 187 LSLICEsNet k_cpu_we_RNIKJPB: 8 loads, 0 LSLICEsNet un1_cen_o_0: 4 loads, 0 LSLICEsNet cpu0/k_ealo_0_sqmuxa_RNICERE1: 5 loads, 5 LSLICEsNet cpu0/k_new_pc26_RNICEI54: 3 loads, 3 LSLICEsNet cpu0/k_ealo_cnv_0[0]: 13 loads, 13 LSLICEsNet cpu0/k_eahi_0_sqmuxa_2_RNIC7377: 4 loads, 4 LSLICEsNet cpu0/k_pp_regs55_RNIJTK99: 2 loads, 2 LSLICEsNet cpu0/un1_state_31_RNIDQAP: 4 loads, 4 LSLICEsNet cpu0/un1_state_28_0_a2_RNIKHLH: 5 loads, 5 LSLICEsNet cpu0/un1_k_opcode_4_RNII2FP8: 8 loads, 8 LSLICEsNet cpu0/k_ofshi_1_sqmuxa_RNI9N8V: 4 loads, 4 LSLICEsNet cpu0/state79_RNICDUH4: 1 loads, 1 LSLICEsNet cpu0/cff_0_sqmuxa_1_i_0_0_RNIAM8L: 44 loads, 44 LSLICEsNet cpu0/regs/eflag_RNO: 1 loads, 1 LSLICEsNet cpu0/regs/IY_0_sqmuxa_i_a3_0_RNI01N31: 18 loads, 18 LSLICEsNet cpu0/regs/IX_0_sqmuxa_1_i_a2_RNIKUBD1: 17 loads, 17 LSLICEsNet cpu0/regs/DP_0_sqmuxa_i_a3_0_RNIV3T11: 7 loads, 7 LSLICEsNet cpu0/regs/ACCB_0_sqmuxa_1_RNIGOBV: 7 loads, 7 LSLICEsNet cpu0/regs/ACCB45_RNI83PT2: 4 loads, 4 LSLICEsNet cpu0/k_memlo_1_sqmuxa_RNIT89Q: 4 loads, 4 LSLICEsNet cpu0/next_state_0_sqmuxa_2_0_a2_RNII5VUC1: 3 loads, 3 LSLICEsNet cpu0/k_new_pc29_RNIV0H41: 4 loads, 4 LSLICEsNet cpu0/un1_state_74_RNIID554: 4 loads, 4 LSLICEsNet cpu0/un3_cpu_reset_RNIO5453: 4 loads, 4 LSLICEsNet cpu0/un3_cpu_reset_RNIT72KK: 4 loads, 4 LSLICEsNet cpu0/un3_cpu_reset_RNIRKP92: 4 loads, 4 LSLICEsNumber of local set/reset loads for net cpu0.cpu_reset_i_2_i merged into GSR: 6Number of LSRs: 2Net cpu0/state_RNI06PR1[5]: 3 loads, 3 LSLICEsNet cpu0/regs/eflag_RNO_0: 1 loads, 1 LSLICEsNumber of nets driven by tri-state buffers: 0Top 10 highest fanout non-clock nets:Net cpu_clk: 211 loadsNet cpu0/dec_o_alu_opcode[0]: 192 loadsNet cpu0/dec_o_alu_opcode[2]: 124 loadsNet cpu0/dec_o_alu_opcode[3]: 104 loadsNet state_o_c[5]: 76 loadsNet state_o_c[1]: 75 loadsNet cpu0/dec_o_p1_mode[0]: 68 loadsNet state_o_c[4]: 65 loadsNet state_o_c[0]: 63 loadsNet state_o_c[3]: 61 loadsNumber of warnings: 3Number of errors: 0Total CPU Time: 1 secsTotal REAL Time: 0 secsPeak Memory Usage: 195 MBDumping design to file P6809_P6809_map.ncd.trce -f "P6809_P6809.mt" -o "P6809_P6809.tw1" "P6809_P6809_map.ncd" "P6809_P6809.prf"trce: version Diamond (64-bit) 2.2.0.101Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Loading design for application trce from file P6809_P6809_map.ncd.Design name: CC3_topNCD version: 3.2Vendor: LATTICEDevice: LCMXO2-7000HEPackage: TQFP144Performance: 4Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.Package Status: Final Version 1.36Performance Hardware Data Status: Final) Version 23.4Setup and Hold Report--------------------------------------------------------------------------------Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101Tue Dec 31 08:52:49 2013Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Report Information------------------Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prfDesign file: P6809_P6809_map.ncdPreference file: P6809_P6809.prfDevice,speed: LCMXO2-7000HE,4Report level: verbose report, limited to 1 item per preference--------------------------------------------------------------------------------BLOCK ASYNCPATHSBLOCK RESETPATHS--------------------------------------------------------------------------------Timing summary (Setup):---------------Timing errors: 4096 Score: 43964214Cumulative negative slack: 43964214Constraints cover 130482274 paths, 1 nets, and 9545 connections (95.7% coverage)--------------------------------------------------------------------------------Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101Tue Dec 31 08:52:49 2013Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Report Information------------------Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prfDesign file: P6809_P6809_map.ncdPreference file: P6809_P6809.prfDevice,speed: LCMXO2-7000HE,MReport level: verbose report, limited to 1 item per preference--------------------------------------------------------------------------------BLOCK ASYNCPATHSBLOCK RESETPATHS--------------------------------------------------------------------------------Timing summary (Hold):---------------Timing errors: 0 Score: 0Cumulative negative slack: 0Constraints cover 130482274 paths, 1 nets, and 9903 connections (99.2% coverage)Timing summary (Setup and Hold):---------------Timing errors: 4096 (setup), 0 (hold)Score: 43964214 (setup), 0 (hold)Cumulative negative slack: 43964214 (43964214+0)----------------------------------------------------------------------------------------------------------------------------------------------------------------Total time: 0 secs
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