Subversion Repositories 6809_6309_compatible_core

synpwrap -prj "P6809_P6809_synplify.tcl" -log "P6809_P6809.srf"
 
*****************************************************************
 
Warning: You are running on an unsupported platform 
  'synplify_pro' only supports Red Hat Enterprise Linux 4.0 and above
 
  current platform: CentOS release 6.4 (Final)
Kernel \r on an \m 
 
*****************************************************************
 
Running in Lattice mode


Starting:    /usr/local/diamond/2.2_x64/synpbase/linux_a_64/mbin/synbatch
Install:     /usr/local/diamond/2.2_x64/synpbase
Date:        Sun Jan  5 08:22:47 2014
Version:     G-2012.09L-SP1 

Arguments:   -product synplify_pro  -batch P6809_P6809_synplify.tcl
ProductType: synplify_pro






log file: "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr"


Running proj_1|P6809

Running Compile on proj_1|P6809

Running Compile Process on proj_1|P6809

Running Compile Input on proj_1|P6809

Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/synwork/P6809_P6809_compiler.srs to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srs

compiler Completed with warnings
Return Code: 1
Run Time:00h:00m:04s


Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srf

Job Compile Process completed on proj_1|P6809

Running Premap on proj_1|P6809

premap Completed with warnings
Return Code: 1
Run Time:00h:00m:01s


Job Compile completed on proj_1|P6809

Running Map on proj_1|P6809

Running Map & Optimize on proj_1|P6809

fpga_mapper Completed with warnings
Return Code: 1
Run Time:00h:00m:17s


Job Map completed on proj_1|P6809

Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srf

Job Logic Synthesis completed on proj_1|P6809

TCL script complete: "P6809_P6809_synplify.tcl"

exit status=0


Copyright (C) 1992-2013 Lattice Semiconductor Corporation. All rights reserved.
Lattice Diamond Version 2.2.0.101
Child process exit with 0.

==contents of P6809_P6809.srf
#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013
#install: /usr/local/diamond/2.2_x64/synpbase
#OS: Linux 
#Hostname: node01.pacito.sys

#Implementation: P6809

$ Start of Compile
#Sun Jan  5 08:22:47 2014

Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
@N|Running in 64-bit mode
Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"
@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"
@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"
@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":698:23:698:27|Specified digits overflow the number's size
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v"
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v"
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v"
Verilog syntax check successful!
File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v changed - recompiling
File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v changed - recompiling
Selecting top level module CC3_top
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":57:7:57:10|Synthesizing module alu8

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":319:0:319:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:5:85:12|No assignment to wire cadd16_w

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:15:85:22|No assignment to wire cadc16_w

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:25:85:32|No assignment to wire csub16_w

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:35:85:42|No assignment to wire csbc16_w

@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":184:12:184:13|No assignment to n8
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":184:20:184:21|No assignment to z8
@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":301:0:301:5|Pruning register regq8[7:0] 

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":650:7:650:12|Synthesizing module mul8x8

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":325:7:325:11|Synthesizing module alu16

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":645:0:645:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":433:12:433:18|No assignment to wire q16_mul

@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":561:0:561:5|Pruning register regq16[15:0] 

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":15:7:15:9|Synthesizing module alu

@W: CS263 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":32:18:32:28|Port-width mismatch for port a_in. Formal has width 16, Actual 8
@W: CS263 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":32:30:32:40|Port-width mismatch for port b_in. Formal has width 16, Actual 8
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":243:0:243:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":131:7:131:15|Synthesizing module decode_op

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":259:7:259:15|Synthesizing module decode_ea

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":285:7:285:16|Synthesizing module decode_alu

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":358:7:358:20|Synthesizing module test_condition

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu

@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":417:6:417:13|Ignoring system task $display
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1033:0:1033:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":64:11:64:23|No assignment to wire alu8_o_result

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":65:11:65:20|No assignment to wire alu8_o_CCR

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit k_mem_dest[0] is always 1, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit k_mem_dest[1] is always 0, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit next_mem_state[1] is always 0, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit next_mem_state[2] is always 0, optimizing ...
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Pruning register bits 2 to 1 of next_mem_state[5:0] 

@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI

@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC

@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k

@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v":8:7:8:13|Synthesizing module fontrom

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":8:7:8:15|Synthesizing module textmem4k

@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":2:7:2:13|Synthesizing module vgatext

@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":133:4:133:11|Ignoring system task $display
@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":167:6:167:11|System task $write is not supported yet
@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":174:6:174:11|System task $write is not supported yet
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":184:0:184:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
@W: CG781 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of redr[3:0] -- not in use ...

@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...

@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...

@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element redr.
@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element greenr.
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":10:7:10:13|Synthesizing module CC3_top

@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":31:14:31:21|No assignment to clk_div2
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|No assignment to wire cpu1_addr_o

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:40:37:51|No assignment to wire cpu1_data_in

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|No assignment to wire cpu1_data_out

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:23:38:29|No assignment to wire cpu1_we

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:32:38:38|No assignment to wire cpu1_oe

@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":105:25:105:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Pruning register bits 5 to 3 of next_push_state[5:0] 

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":362:18:362:20|Input port bits 7 to 4 of CCR[7:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":287:18:287:26|Input port bits 5 to 4 of postbyte0[7:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":260:18:260:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":329:18:329:20|Input port bits 7 to 4 of CCR[7:0] are unused

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":660:0:660:5|Pruning register bits 15 to 13 of pipe0[15:0] 

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":660:0:660:5|Register bit pipe0[12] is always 0, optimizing ...
@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":660:0:660:5|Pruning register bit 12 of pipe0[12:0] 

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":59:19:59:22|Input port bits 15 to 8 of a_in[15:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":60:19:60:22|Input port bits 15 to 8 of b_in[15:0] are unused

@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":58:12:58:17|Input clk_in is unused
@END
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Sun Jan  5 08:22:49 2014

###########################################################]
Premap Report

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version G-2012.09L-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)

@L: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt 
Printing clock  summary report in "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 95MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 95MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 111MB)



Clock Summary
**************

Start                             Requested     Requested     Clock                              Clock              
Clock                             Frequency     Period        Type                               Group              
--------------------------------------------------------------------------------------------------------------------
CC3_top|clk40_i                   1.0 MHz       1000.000      inferred                           Inferred_clkgroup_0
CC3_top|cpu_clk_derived_clock     1.0 MHz       1000.000      derived (from CC3_top|clk40_i)     Inferred_clkgroup_0
====================================================================================================================

@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 83 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

syn_allowed_resources : blockrams=26  set on top level netlist CC3_top
Finished Pre Mapping Phase.Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 136MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Jan  5 08:22:51 2014

###########################################################]
Map & Optimize Report

Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version G-2012.09L-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)

@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)


Available hyper_sources - for debug and ip models
        None Found


Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Found counter in view:work.regblock(verilog) inst PC[15:0]
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 

Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 154MB peak: 157MB)

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs 

Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 158MB)



Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 158MB)

@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":237:2:237:3|Pipelining module un1_ea_reg_2[15:0]
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register SU[15:0] pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register k_ind_ea[7:0] pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register SS[15:0] pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register IX[15:0] pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register IY[15:0] pushed in.
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":253:2:253:5|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.k_new_pc_4[15:0] from cpu0.un1_regs_o_pc[15:0] 

Starting Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 149MB peak: 158MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 149MB peak: 158MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 149MB peak: 158MB)


Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 148MB peak: 158MB)


Finished technology mapping (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 197MB peak: 226MB)

Pass             CPU time               Worst Slack             Luts / Registers
------------------------------------------------------------
Pass             CPU time               Worst Slack             Luts / Registers
------------------------------------------------------------
------------------------------------------------------------


Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 165MB peak: 226MB)

@N: FX164 |The option to pack flops in the IOB has not been specified 

Finished restoring hierarchy (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 166MB peak: 226MB)



#### START OF CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 504 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
281 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0001       clk40_i             port                   504        cpu_clk        
=======================================================================================
===== Gated/Generated Clocks =====
************** None **************
----------------------------------
==================================


##### END OF CLOCK OPTIMIZATION REPORT ######]

Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 169MB peak: 226MB)

Writing EDIF Netlist and constraint files
G-2012.09L-SP1 
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 173MB peak: 226MB)

@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"



##### START OF TIMING REPORT #####[
# Timing Report written on Sun Jan  5 08:23:08 2014
#


Top view:               CC3_top
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 979.333

                    Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock      Frequency     Frequency     Period        Period        Slack       Type         Group              
------------------------------------------------------------------------------------------------------------------------
CC3_top|clk40_i     1.0 MHz       48.4 MHz      1000.000      20.667        979.333     inferred     Inferred_clkgroup_0
========================================================================================================================





Clock Relationships
*******************

Clocks                            |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------------
Starting         Ending           |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------------------------
CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    979.333  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: CC3_top|clk40_i
====================================



Starting Points with Worst Slack
********************************

                         Starting                                                       Arrival            
Instance                 Reference           Type        Pin     Net                    Time        Slack  
                         Clock                                                                             
-----------------------------------------------------------------------------------------------------------
cpu0.regs.SU_pipe_21     CC3_top|clk40_i     FD1P3AX     Q       un1_ea_reg_sn_N_3f     1.268       979.333
cpu0.regs.SS_pipe_20     CC3_top|clk40_i     FD1P3AX     Q       SS_pipe_20             1.268       979.397
cpu0.regs.SU_pipe_19     CC3_top|clk40_i     FD1P3AX     Q       SU_pipe_19             1.044       979.557
cpu0.regs.SU_pipe_20     CC3_top|clk40_i     FD1P3AX     Q       SU_pipe_20             1.044       979.557
cpu0.k_opcode[1]         CC3_top|clk40_i     FD1P3AX     Q       k_opcode[1]            1.387       979.562
cpu0.k_opcode[0]         CC3_top|clk40_i     FD1P3AX     Q       k_opcode[0]            1.358       979.591
cpu0.regs.SS_pipe_18     CC3_top|clk40_i     FD1P3AX     Q       un1_SS_m1f[0]          1.044       979.621
cpu0.regs.SS_pipe_19     CC3_top|clk40_i     FD1P3AX     Q       un1_SS_m0f[0]          1.044       979.621
cpu0.regs.SS_pipe_21     CC3_top|clk40_i     FD1P3AX     Q       un1_SS_m1f[1]          0.972       979.908
cpu0.regs.SS_pipe_22     CC3_top|clk40_i     FD1P3AX     Q       un1_SS_m0f[1]          0.972       979.908
===========================================================================================================


Ending Points with Worst Slack
******************************

                     Starting                                             Required            
Instance             Reference           Type        Pin     Net          Time         Slack  
                     Clock                                                                    
----------------------------------------------------------------------------------------------
cpu0.regs.PC[14]     CC3_top|clk40_i     FD1P3AX     D       PC_s[14]     999.894      979.333
cpu0.regs.PC[15]     CC3_top|clk40_i     FD1P3AX     D       PC_s[15]     999.894      979.333
cpu0.regs.PC[12]     CC3_top|clk40_i     FD1P3AX     D       PC_s[12]     999.894      979.476
cpu0.regs.PC[13]     CC3_top|clk40_i     FD1P3AX     D       PC_s[13]     999.894      979.476
cpu0.regs.PC[10]     CC3_top|clk40_i     FD1P3AX     D       PC_s[10]     999.894      979.619
cpu0.regs.PC[11]     CC3_top|clk40_i     FD1P3AX     D       PC_s[11]     999.894      979.619
cpu0.regs.PC[8]      CC3_top|clk40_i     FD1P3AX     D       PC_s[8]      999.894      979.794
cpu0.regs.PC[9]      CC3_top|clk40_i     FD1P3AX     D       PC_s[9]      999.894      979.794
cpu0.regs.PC[6]      CC3_top|clk40_i     FD1P3AX     D       PC_s[6]      999.894      979.937
cpu0.regs.PC[7]      CC3_top|clk40_i     FD1P3AX     D       PC_s[7]      999.894      979.937
==============================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         999.894

    - Propagation time:                      20.561
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     979.333

    Number of logic level(s):                21
    Starting point:                          cpu0.regs.SU_pipe_21 / Q
    Ending point:                            cpu0.regs.PC[15] / D
    The start point is clocked by            CC3_top|clk40_i [rising] on pin CK
    The end   point is clocked by            CC3_top|clk40_i [rising] on pin CK

Instance / Net                                        Pin      Pin               Arrival     No. of    
Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
cpu0.regs.SU_pipe_21                     FD1P3AX      Q        Out     1.268     1.268       -         
un1_ea_reg_sn_N_3f                       Net          -        -       -         -           17        
cpu0.regs.un1_ea_reg[0]                  ORCALUT4     C        In      0.000     1.268       -         
cpu0.regs.un1_ea_reg[0]                  ORCALUT4     Z        Out     1.153     2.421       -         
N_289                                    Net          -        -       -         -           3         
cpu0.regs.un1_ea_reg_2_cry_0_0           CCU2D        B1       In      0.000     2.421       -         
cpu0.regs.un1_ea_reg_2_cry_0_0           CCU2D        COUT     Out     1.544     3.965       -         
un1_ea_reg_2_cry_0                       Net          -        -       -         -           1         
cpu0.regs.un1_ea_reg_2_cry_1_0           CCU2D        CIN      In      0.000     3.965       -         
cpu0.regs.un1_ea_reg_2_cry_1_0           CCU2D        S1       Out     1.765     5.730       -         
SU[2]                                    Net          -        -       -         -           6         
cpu0.regs.ea_reg_3_am[2]                 ORCALUT4     C        In      0.000     5.730       -         
cpu0.regs.ea_reg_3_am[2]                 ORCALUT4     Z        Out     1.017     6.747       -         
ea_reg_3_am[2]                           Net          -        -       -         -           1         
cpu0.regs.ea_reg_3[2]                    PFUMX        BLUT     In      0.000     6.747       -         
cpu0.regs.ea_reg_3[2]                    PFUMX        Z        Out     0.390     7.137       -         
ea_reg[2]                                Net          -        -       -         -           4         
cpu0.regs.un1_PC_1_0[2]                  ORCALUT4     A        In      0.000     7.137       -         
cpu0.regs.un1_PC_1_0[2]                  ORCALUT4     Z        Out     1.017     8.154       -         
N_506                                    Net          -        -       -         -           1         
cpu0.regs.eamem_addr_cry_1_0             CCU2D        C1       In      0.000     8.154       -         
cpu0.regs.eamem_addr_cry_1_0             CCU2D        COUT     Out     1.544     9.698       -         
eamem_addr_cry_2                         Net          -        -       -         -           1         
cpu0.regs.eamem_addr_cry_3_0             CCU2D        CIN      In      0.000     9.698       -         
cpu0.regs.eamem_addr_cry_3_0             CCU2D        COUT     Out     0.143     9.841       -         
eamem_addr_cry_4                         Net          -        -       -         -           1         
cpu0.regs.eamem_addr_cry_5_0             CCU2D        CIN      In      0.000     9.841       -         
cpu0.regs.eamem_addr_cry_5_0             CCU2D        COUT     Out     0.143     9.984       -         
eamem_addr_cry_6                         Net          -        -       -         -           1         
cpu0.regs.eamem_addr_cry_7_0             CCU2D        CIN      In      0.000     9.984       -         
cpu0.regs.eamem_addr_cry_7_0             CCU2D        COUT     Out     0.143     10.127      -         
eamem_addr_cry_8                         Net          -        -       -         -           1         
cpu0.regs.eamem_addr_cry_9_0             CCU2D        CIN      In      0.000     10.127      -         
cpu0.regs.eamem_addr_cry_9_0             CCU2D        S0       Out     1.685     11.812      -         
regs_o_eamem_addr[9]                     Net          -        -       -         -           3         
cpu0.regs.eamem_addr_cry_9_0_RNISAU9     ORCALUT4     A        In      0.000     11.812      -         
cpu0.regs.eamem_addr_cry_9_0_RNISAU9     ORCALUT4     Z        Out     1.089     12.901      -         
datamux_o_dest_6[9]                      Net          -        -       -         -           2         
cpu0.regs.k_new_pc_1[9]                  ORCALUT4     A        In      0.000     12.901      -         
cpu0.regs.k_new_pc_1[9]                  ORCALUT4     Z        Out     1.017     13.917      -         
N_953                                    Net          -        -       -         -           1         
cpu0.regs.k_new_pc_2[9]                  ORCALUT4     A        In      0.000     13.917      -         
cpu0.regs.k_new_pc_2[9]                  ORCALUT4     Z        Out     1.017     14.934      -         
N_969                                    Net          -        -       -         -           1         
cpu0.regs.k_new_pc_5[9]                  ORCALUT4     A        In      0.000     14.934      -         
cpu0.regs.k_new_pc_5[9]                  ORCALUT4     Z        Out     1.017     15.951      -         
k_new_pc[9]                              Net          -        -       -         -           1         
cpu0.regs.PC_11_am[9]                    ORCALUT4     A        In      0.000     15.951      -         
cpu0.regs.PC_11_am[9]                    ORCALUT4     Z        Out     1.017     16.968      -         
PC_11_am[9]                              Net          -        -       -         -           1         
cpu0.regs.PC_11[9]                       PFUMX        BLUT     In      0.000     16.968      -         
cpu0.regs.PC_11[9]                       PFUMX        Z        Out     0.214     17.182      -         
PC_11[9]                                 Net          -        -       -         -           1         
cpu0.regs.PC_cry_0[8]                    CCU2D        B1       In      0.000     17.182      -         
cpu0.regs.PC_cry_0[8]                    CCU2D        COUT     Out     1.544     18.727      -         
PC_cry[9]                                Net          -        -       -         -           1         
cpu0.regs.PC_cry_0[10]                   CCU2D        CIN      In      0.000     18.727      -         
cpu0.regs.PC_cry_0[10]                   CCU2D        COUT     Out     0.143     18.869      -         
PC_cry[11]                               Net          -        -       -         -           1         
cpu0.regs.PC_cry_0[12]                   CCU2D        CIN      In      0.000     18.869      -         
cpu0.regs.PC_cry_0[12]                   CCU2D        COUT     Out     0.143     19.012      -         
PC_cry[13]                               Net          -        -       -         -           1         
cpu0.regs.PC_cry_0[14]                   CCU2D        CIN      In      0.000     19.012      -         
cpu0.regs.PC_cry_0[14]                   CCU2D        S1       Out     1.549     20.561      -         
PC_s[15]                                 Net          -        -       -         -           1         
cpu0.regs.PC[15]                         FD1P3AX      D        In      0.000     20.561      -         
=======================================================================================================



##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report
Part: lcmxo2_7000he-4

Register bits: 488 of 6864 (7%)
PIC Latch:       0
I/O cells:       49
Block Rams : 10 of 26 (38%)


Details:
CCU2D:          196
DP8KC:          10
FD1P3AX:        441
FD1P3DX:        6
FD1P3IX:        1
FD1S3AX:        28
FD1S3IX:        2
GSR:            1
IB:             1
INV:            20
L6MUX21:        37
OB:             40
OBZ:            8
OFS1P3DX:       9
OFS1P3IX:       1
ORCALUT4:       2025
PFUMX:          273
PUR:            1
VHI:            10
VLO:            16
true:           6
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 43MB peak: 226MB)

Process took 0h:00m:16s realtime, 0h:00m:16s cputime
# Sun Jan  5 08:23:08 2014

###########################################################]


Synthesis exit by 0.

edif2ngd  -l "MachXO2" -d LCMXO2-7000HE -path "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -path "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice"  "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi" "P6809_P6809.ngo"   
edif2ngd:  version Diamond (64-bit) 2.2.0.101

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...
  On or above line 310 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...
  On or above line 318 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 1832 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 4556 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 9109 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 9904 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 10621 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 10919 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 11654 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 12094 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 13053 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 15901 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 28685 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 31454 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 34211 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 34629 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 40141 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
  On or above line 40954 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

Writing the design to P6809_P6809.ngo...


ngdbuild  -a "MachXO2" -d LCMXO2-7000HE  -p "/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data"  -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice"  "P6809_P6809.ngo" "P6809_P6809.ngd"          
ngdbuild:  version Diamond (64-bit) 2.2.0.101

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
Reading 'P6809_P6809.ngo' ...
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/or5g00/data/orc5glib.ngl'...


Running DRC...

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_s_15_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_s_15_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_cry_0_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_8_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_1_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_1_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_8_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_1_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_1_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_8_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_1_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_1_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sbc16_w_cry_15_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sbc16_w_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sub16_w_cry_15_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sub16_w_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sub16_w_cry_0_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/add16_w_cry_15_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/add16_w_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/add16_w_cry_0_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_s_15_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_s_15_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_13_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_13_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_11_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_11_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_9_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_9_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_7_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_7_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_5_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_5_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_3_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_3_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_1_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_1_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_0_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sub8_w_cry_7_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sub8_w_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sub8_w_cry_0_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sbc8_w_cry_7_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sbc8_w_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/add8_w_cry_7_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/add8_w_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/add8_w_cry_0_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_s_7_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_s_7_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_5_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_5_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_3_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_3_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_1_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_1_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_0_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_s_15_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_s_15_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_cry_0_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_s_15_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_s_15_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_cry_0_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_s_15_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_s_15_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_cry_0_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_s_15_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_s_15_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_cry_0_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_s_15_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_s_15_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_cry_0_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/PC_cry_0_COUT[14]' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/PC_lcry_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/regs/PC_lcry_0_S1' has no load
WARNING - ngdbuild: logical net 'textctrl/yptr_5_s_6_0_COUT' has no load
WARNING - ngdbuild: logical net 'textctrl/yptr_5_s_6_0_S1' has no load
WARNING - ngdbuild: logical net 'textctrl/yptr_5_cry_1_0_S0' has no load
WARNING - ngdbuild: logical net 'textctrl/yptr_5_cry_1_0_S1' has no load
WARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_7_0_COUT' has no load
WARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_2_0_S0' has no load
WARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_2_0_S1' has no load
WARNING - ngdbuild: logical net 'textctrl/yptr_cry_10_0_COUT' has no load
WARNING - ngdbuild: logical net 'textctrl/yptr_cry_5_0_S0' has no load
WARNING - ngdbuild: logical net 'textctrl/yptr_cry_5_0_S1' has no load
WARNING - ngdbuild: logical net 'textctrl/x_cnt_cry_0_COUT[5]' has no load
WARNING - ngdbuild: logical net 'textctrl/x_cnt_cry_0_S0[0]' has no load
WARNING - ngdbuild: logical net 'textctrl/y_cnt_cry_0_COUT[5]' has no load
WARNING - ngdbuild: logical net 'textctrl/y_cnt_cry_0_S0[0]' has no load
WARNING - ngdbuild: logical net 'textctrl/vsync_cnt_cry_0_COUT[9]' has no load
WARNING - ngdbuild: logical net 'textctrl/vsync_cnt_cry_0_S0[0]' has no load
WARNING - ngdbuild: logical net 'textctrl/blink_cnt_s_0_COUT[5]' has no load
WARNING - ngdbuild: logical net 'textctrl/blink_cnt_s_0_S1[5]' has no load
WARNING - ngdbuild: logical net 'textctrl/blink_cnt_cry_0_S0[0]' has no load
WARNING - ngdbuild: logical net 'textctrl/hsync_cnt_cry_0_COUT[9]' has no load
WARNING - ngdbuild: logical net 'textctrl/hsync_cnt_cry_0_S0[0]' has no load
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_COUT' has no load
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_S1' has no load
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S0' has no load
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S1' has no load
WARNING - ngdbuild: DRC complete with 117 warnings

Design Results:
   3125 blocks expanded
complete the first expansion
Writing 'P6809_P6809.ngd' ...

map -a "MachXO2" -p LCMXO2-7000HE -t TQFP144 -s 4 -oc Commercial   "P6809_P6809.ngd" -o "P6809_P6809_map.ncd" -pr "P6809_P6809.prf" -mp "P6809_P6809.mrp" "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809.lpf" -c 0            
map:  version Diamond (64-bit) 2.2.0.101

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
   Process the file: P6809_P6809.ngd
   Picdevice="LCMXO2-7000HE"

   Pictype="TQFP144"

   Picspeed=4

   Remove unused logic

   Do not produce over sized NCDs.

Part used: LCMXO2-7000HETQFP144, Performance used: 4.
Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
Package Status:                     Final          Version 1.36

Running general design DRC...
Removing unused logic...
Optimizing...
7 CCU2 constant inputs absorbed.
WARNING - map: Using local reset signal 'reset_o_c' to infer global GSR net.
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_0_3' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_1_2' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_2_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_3_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_0_3' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_1_2' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_2_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_3_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
WARNING - map: The reset of EBR 'bios/bios2k_0_1_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
WARNING - map: The reset of EBR 'bios/bios2k_0_0_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.



Design Summary:
   Number of registers:    488
      PFU registers:    478
      PIO registers:    10
   Number of SLICEs:          1219 out of  3432 (36%)
      SLICEs(logic/ROM):       858 out of   858 (100%)
      SLICEs(logic/ROM/RAM):   361 out of  2574 (14%)
          As RAM:            0 out of  2574 (0%)
          As Logic/ROM:    361 out of  2574 (14%)
   Number of logic LUT4s:     2044
   Number of distributed RAM:   0 (0 LUT4s)
   Number of ripple logic:    196 (392 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:     2436
   Number of PIO sites used: 49 + 4(JTAG) out of 115 (46%)
   Number of block RAMs:  10 out of 26 (38%)
   Number of GSRs:  1 out of 1 (100%)
   EFB used :       No
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   POR :            On
   Bandgap :        On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 6 (0%)
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Number of PLLs:  0 out of 2 (0%)
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of CLKDIVC:  0 out of 4 (0%)
   Number of ECLKSYNCA:  0 out of 4 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
   Number of clocks:  1
     Net cpu_clkgen: 305 loads, 305 rising, 0 falling (Driver: PIO clk40_i )
   Number of Clock Enables:  35
     Net cpu_clk: 97 loads, 97 LSLICEs
     Net leds_r_cnv[0]: 8 loads, 0 LSLICEs
     Net textctrl/un1_CPU_OE_EN_0_a2: 8 loads, 0 LSLICEs
     Net textctrl/line_cnte: 2 loads, 2 LSLICEs
     Net textctrl/y_cnte: 4 loads, 4 LSLICEs
     Net textctrl/x_cnte: 4 loads, 4 LSLICEs
     Net textctrl/N_4: 6 loads, 6 LSLICEs
     Net textctrl/tshift_1_sqmuxa: 4 loads, 4 LSLICEs
     Net textctrl/N_103_i_0: 4 loads, 4 LSLICEs
     Net textctrl/vsync_cnt_0_sqmuxa_4: 4 loads, 4 LSLICEs
     Net un1_bios_en_0_a2: 4 loads, 0 LSLICEs
     Net cpu0/un1_state_23_RNIKLF8L: 3 loads, 3 LSLICEs
     Net cpu0/un1_state_53_RNIKL6IT: 4 loads, 4 LSLICEs
     Net cpu0/k_memhi_0_sqmuxa_RNIS2L63: 4 loads, 4 LSLICEs
     Net cpu0/k_ealo_cnv_0[0]: 16 loads, 16 LSLICEs
     Net cpu0/un1_state_12_1_RNIGGP7P: 4 loads, 4 LSLICEs
     Net cpu0/un1_cpu_reset_6_0_a3_1_RNI3DL77: 3 loads, 3 LSLICEs
     Net cpu0/next_state10_RNIVT0PU: 2 loads, 2 LSLICEs
     Net cpu0/un1_dest_reg44_1_0_a2_1_0_RNIUSPTD1: 8 loads, 8 LSLICEs
     Net cpu0/un1_cpu_reset_5_0_a3_2_RNIUKBUL: 2 loads, 2 LSLICEs
     Net cpu0/un1_state_82_1_RNICEGM2: 4 loads, 4 LSLICEs
     Net cpu0/un1_cpu_reset_10_0_a3_0_0_RNIDMV84: 2 loads, 2 LSLICEs
     Net cpu0/regs/eflag_RNO: 1 loads, 1 LSLICEs
     Net cpu0/un1_state_18_2_RNI7CC51: 4 loads, 4 LSLICEs
     Net cpu0/un1_state_56_RNI0KNU2: 8 loads, 8 LSLICEs
     Net cpu0/regs/cff_0_sqmuxa_1_0_RNI212L: 7 loads, 7 LSLICEs
     Net cpu0/regs/IY_0_sqmuxa_1_RNI1CVH1: 17 loads, 17 LSLICEs
     Net cpu0/regs/IX_0_sqmuxa_1_1_RNIGA2K1: 19 loads, 19 LSLICEs
     Net cpu0/regs/DP_1_sqmuxa_0_RNI70L71: 5 loads, 5 LSLICEs
     Net cpu0/regs/ACCB_0_sqmuxa_1_RNIHOBV: 4 loads, 4 LSLICEs
     Net cpu0/regs/ACCB45_RNIMT5N2: 4 loads, 4 LSLICEs
     Net cpu0/un1_state_18_2_RNI3MPQ: 4 loads, 4 LSLICEs
     Net cpu0/k_ofshi_cnv[0]: 4 loads, 4 LSLICEs
     Net cpu0/state_RNIGVAO2[5]: 4 loads, 4 LSLICEs
     Net cpu0/un1_state_84_1_RNITNQJ9: 4 loads, 4 LSLICEs
   Number of local set/reset loads for net reset_o_c merged into GSR:  6
   Number of LSRs:  2
     Net textctrl.vsync_cnt[10]: 3 loads, 2 LSLICEs
     Net cpu0/G_7: 1 loads, 1 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net cpu_clk: 117 loads
     Net state_o_c[1]: 103 loads
     Net cpu0/dec_o_alu_opcode[0]: 92 loads
     Net state_o_c[4]: 81 loads
     Net state_o_c[2]: 74 loads
     Net cpu0/k_opcode[1]: 72 loads
     Net cpu0/dec_o_p1_mode[0]: 70 loads
     Net cpu0/dec_o_alu_opcode[4]: 66 loads
     Net cpu0/dec_o_alu_opcode[3]: 63 loads
     Net cpu0/k_opcode[3]: 63 loads
 
   Number of warnings:  11
   Number of errors:    0


Total CPU Time: 0 secs  
Total REAL Time: 0 secs  
Peak Memory Usage: 195 MB

Dumping design to file P6809_P6809_map.ncd.

trce -f "P6809_P6809.mt" -o "P6809_P6809.tw1" "P6809_P6809_map.ncd" "P6809_P6809.prf"
trce:  version Diamond (64-bit) 2.2.0.101

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.

Loading design for application trce from file P6809_P6809_map.ncd.
Design name: CC3_top
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-7000HE
Package:     TQFP144
Performance: 4
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
Package Status:                     Final          Version 1.36
Performance Hardware Data Status:   Final)         Version 23.4
Setup and Hold Report

--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
Sun Jan  5 08:23:12 2014

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf 
Design file:     P6809_P6809_map.ncd
Preference file: P6809_P6809.prf
Device,speed:    LCMXO2-7000HE,4
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



Timing summary (Setup):
---------------

Timing errors: 1702  Score: 686102
Cumulative negative slack: 686102

Constraints cover 3270002 paths, 1 nets, and 9158 connections (96.1% coverage)

--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
Sun Jan  5 08:23:12 2014

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf 
Design file:     P6809_P6809_map.ncd
Preference file: P6809_P6809.prf
Device,speed:    LCMXO2-7000HE,M
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



Timing summary (Hold):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 3270002 paths, 1 nets, and 9437 connections (99.1% coverage)



Timing summary (Setup and Hold):
---------------

Timing errors: 1702 (setup), 0 (hold)
Score: 686102 (setup), 0 (hold)
Cumulative negative slack: 686102 (686102+0)
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------

Total time: 0 secs 

mpartrce -p "P6809_P6809.p2t" -f "P6809_P6809.p3t" -tf "P6809_P6809.pt" "P6809_P6809_map.ncd" "P6809_P6809.ncd"

---- MParTrce Tool ----
Removing old design directory at request of -rem command line option to this program.
Running par. Please wait . . .

Lattice Place and Route Report for Design "P6809_P6809_map.ncd"
Sun Jan  5 08:23:12 2014

PAR: Place And Route Diamond (64-bit) 2.2.0.101.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF P6809_P6809_map.ncd P6809_P6809.dir/5_1.ncd P6809_P6809.prf
Preference file: P6809_P6809.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file P6809_P6809_map.ncd.
Design name: CC3_top
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-7000HE
Package:     TQFP144
Performance: 4
Loading device for application par from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
Package Status:                     Final          Version 1.36
Performance Hardware Data Status:   Final)         Version 23.4
License checked out.


Ignore Preference Error(s):  True
Device utilization summary:

   PIO (prelim)   49+4(JTAG)/336     14% used
                  49+4(JTAG)/115     42% bonded
   IOLOGIC           10/336           2% used

   SLICE           1219/3432         35% used

   GSR                1/1           100% used
   EBR               10/26           38% used


INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.
INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
Number of Signals: 2800
Number of Connections: 9525

Pin Constraint Summary:
   49 out of 49 pins locked (100% locked).

The following 1 signal is selected to use the primary clock routing resources:
    cpu_clkgen (driver: clk40_i, clk load #: 305)


The following 4 signals are selected to use the secondary clock routing resources:
    cpu_clk (driver: SLICE_407, clk load #: 0, sr load #: 0, ce load #: 97)
    cpu0/regs/IX_0_sqmuxa_1_1_RNIGA2K1 (driver: cpu0/SLICE_803, clk load #: 0, sr load #: 0, ce load #: 19)
    cpu0/regs/IY_0_sqmuxa_1_RNI1CVH1 (driver: cpu0/SLICE_804, clk load #: 0, sr load #: 0, ce load #: 17)
    cpu0/k_ealo_cnv_0[0] (driver: cpu0/SLICE_793, clk load #: 0, sr load #: 0, ce load #: 16)

Signal reset_o_c is selected as Global Set/Reset.
Starting Placer Phase 0.
...........
Finished Placer Phase 0.  REAL time: 5 secs 

Starting Placer Phase 1.
......................
Placer score = 869535.
Finished Placer Phase 1.  REAL time: 13 secs 

Starting Placer Phase 2.
.
Placer score =  857738
Finished Placer Phase 2.  REAL time: 14 secs 


------------------ Clock Report ------------------

Global Clock Resources:
  CLK_PIN    : 1 out of 8 (12%)
  PLL        : 0 out of 2 (0%)
  DCM        : 0 out of 2 (0%)
  DCC        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "cpu_clkgen" from comp "clk40_i" on CLK_PIN site "27 (PL22A)", clk load = 305
  SECONDARY "cpu_clk" from Q0 on comp "SLICE_407" on site "R21C20C", clk load = 0, ce load = 97, sr load = 0
  SECONDARY "cpu0/k_ealo_cnv_0[0]" from F1 on comp "cpu0/SLICE_793" on site "R25C35A", clk load = 0, ce load = 16, sr load = 0
  SECONDARY "cpu0/regs/IY_0_sqmuxa_1_RNI1CVH1" from F1 on comp "cpu0/SLICE_804" on site "R14C20A", clk load = 0, ce load = 17, sr load = 0
  SECONDARY "cpu0/regs/IX_0_sqmuxa_1_1_RNIGA2K1" from F1 on comp "cpu0/SLICE_803" on site "R14C18D", clk load = 0, ce load = 19, sr load = 0

  PRIMARY  : 1 out of 8 (12%)
  SECONDARY: 4 out of 8 (50%)

Edge Clocks:
  No edge clock selected.

--------------- End of Clock Report ---------------


I/O Usage Summary (final):
   49 out of 336 (14.6%) PIO sites used.
   49 out of 115 (42.6%) bonded PIO sites used.
   Number of PIO comps: 49; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0        | 12 / 28 ( 42%) | 2.5V       | -         |
| 1        | 13 / 29 ( 44%) | 2.5V       | -         |
| 2        | 23 / 29 ( 79%) | 2.5V       | -         |
| 3        | 1 / 9 ( 11%)   | 2.5V       | -         |
| 4        | 0 / 10 (  0%)  | -          | -         |
| 5        | 0 / 10 (  0%)  | -          | -         |
+----------+----------------+------------+-----------+

Total placer CPU time: 13 secs 

Dumping design to file P6809_P6809.dir/5_1.ncd.

0 connections routed; 9525 unrouted.
Starting router resource preassignment

Completed router resource preassignment. Real time: 17 secs 

Start NBR router at Sun Jan 05 08:23:29 CET 2014

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in TRCE report. You should always run TRCE to verify  
      your design. Thanks.                                       
*****************************************************************

Start NBR special constraint process at Sun Jan 05 08:23:29 CET 2014

Start NBR section for initial routing
Level 1, iteration 1
126(0.03%) conflicts; 8022(84.22%) untouched conns; 0 (nbr) score; 
Estimated worst slack/total negative slack: 0.040ns/0.000ns; real time: 19 secs 
Level 2, iteration 1
102(0.03%) conflicts; 7583(79.61%) untouched conns; 0 (nbr) score; 
Estimated worst slack/total negative slack: 0.119ns/0.000ns; real time: 20 secs 
Level 3, iteration 1
64(0.02%) conflicts; 5994(62.93%) untouched conns; 0 (nbr) score; 
Estimated worst slack/total negative slack: 0.026ns/0.000ns; real time: 21 secs 
Level 4, iteration 1
315(0.08%) conflicts; 0(0.00%) untouched conn; 58 (nbr) score; 
Estimated worst slack/total negative slack: -0.003ns/-0.058ns; real time: 22 secs 

Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area  at 75% usage is 24 (2.40%)

Start NBR section for normal routing
Level 1, iteration 1
21(0.01%) conflicts; 420(4.41%) untouched conns; 0 (nbr) score; 
Estimated worst slack/total negative slack: 0.064ns/0.000ns; real time: 23 secs 
Level 2, iteration 1
17(0.00%) conflicts; 420(4.41%) untouched conns; 0 (nbr) score; 
Estimated worst slack/total negative slack: 0.064ns/0.000ns; real time: 23 secs 
Level 3, iteration 1
22(0.01%) conflicts; 410(4.30%) untouched conns; 0 (nbr) score; 
Estimated worst slack/total negative slack: 0.064ns/0.000ns; real time: 23 secs 
Level 4, iteration 1
171(0.05%) conflicts; 0(0.00%) untouched conn; 59 (nbr) score; 
Estimated worst slack/total negative slack: -0.003ns/-0.059ns; real time: 24 secs 
Level 4, iteration 2
101(0.03%) conflicts; 0(0.00%) untouched conn; 97 (nbr) score; 
Estimated worst slack/total negative slack: -0.005ns/-0.097ns; real time: 24 secs 
Level 4, iteration 3
61(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack: 0.001ns/0.000ns; real time: 24 secs 
Level 4, iteration 4
39(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack: 0.001ns/0.000ns; real time: 25 secs 
Level 4, iteration 5
11(0.00%) conflicts; 0(0.00%) untouched conn; 2436 (nbr) score; 
Estimated worst slack/total negative slack: -0.101ns/-2.436ns; real time: 25 secs 
Level 4, iteration 6
7(0.00%) conflicts; 0(0.00%) untouched conn; 2436 (nbr) score; 
Estimated worst slack/total negative slack: -0.101ns/-2.436ns; real time: 25 secs 
Level 4, iteration 7
3(0.00%) conflicts; 0(0.00%) untouched conn; 2252 (nbr) score; 
Estimated worst slack/total negative slack: -0.094ns/-2.252ns; real time: 25 secs 
Level 4, iteration 8
3(0.00%) conflicts; 0(0.00%) untouched conn; 2252 (nbr) score; 
Estimated worst slack/total negative slack: -0.094ns/-2.252ns; real time: 25 secs 
Level 4, iteration 9
1(0.00%) conflict; 0(0.00%) untouched conn; 2316 (nbr) score; 
Estimated worst slack/total negative slack: -0.094ns/-2.316ns; real time: 25 secs 
Level 4, iteration 10
0(0.00%) conflict; 0(0.00%) untouched conn; 2316 (nbr) score; 
Estimated worst slack/total negative slack: -0.094ns/-2.316ns; real time: 25 secs 

Start NBR section for performance tunning (iteration 1)
Level 4, iteration 1
2(0.00%) conflicts; 0(0.00%) untouched conn; 1916 (nbr) score; 
Estimated worst slack/total negative slack: -0.094ns/-1.916ns; real time: 26 secs 
Level 4, iteration 2
2(0.00%) conflicts; 0(0.00%) untouched conn; 1916 (nbr) score; 
Estimated worst slack/total negative slack: -0.094ns/-1.916ns; real time: 26 secs 
Level 4, iteration 3
1(0.00%) conflict; 0(0.00%) untouched conn; 2316 (nbr) score; 
Estimated worst slack/total negative slack: -0.094ns/-2.316ns; real time: 26 secs 
Level 4, iteration 4
0(0.00%) conflict; 0(0.00%) untouched conn; 2316 (nbr) score; 
Estimated worst slack/total negative slack: -0.094ns/-2.316ns; real time: 26 secs 

Start NBR section for re-routing
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 2316 (nbr) score; 
Estimated worst slack/total negative slack: -0.094ns/-2.316ns; real time: 26 secs 

Start NBR section for post-routing

End NBR router with 0 unrouted connection

NBR Summary
-----------
  Number of unrouted connections : 0 (0.00%)
  Number of connections with timing violations : 28 (0.29%)
  Estimated worst slack : -0.094ns
  Timing score : 281
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.



------------------------------------------------------------------------------------------------------------------------------------
WARNING - par: Hold timing correction is skipped because the worst (setup) slack(-0.094ns) is worse than the default value(0.000ns).
------------------------------------------------------------------------------------------------------------------------------------

Total CPU time 26 secs 
Total REAL time: 27 secs 
Completely routed.
End of route.  9525 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.

Hold time timing score: 0, hold timing errors: 0

Timing score: 281 

Dumping design to file P6809_P6809.dir/5_1.ncd.


PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack<setup/<ns>> = -0.094
PAR_SUMMARY::Timing score<setup/<ns>> = 0.281
PAR_SUMMARY::Worst  slack<hold /<ns>> = <n/a>
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>

Total CPU  time to completion: 27 secs 
Total REAL time to completion: 28 secs 

par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
Exiting par with exit code 0
Exiting mpartrce with exit code 0

trce -f "P6809_P6809.pt" -o "P6809_P6809.twr" "P6809_P6809.ncd" "P6809_P6809.prf"
trce:  version Diamond (64-bit) 2.2.0.101

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.

Loading design for application trce from file P6809_P6809.ncd.
Design name: CC3_top
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-7000HE
Package:     TQFP144
Performance: 4
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
Package Status:                     Final          Version 1.36
Performance Hardware Data Status:   Final)         Version 23.4
Setup and Hold Report

--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
Sun Jan  5 08:23:43 2014

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf 
Design file:     P6809_P6809.ncd
Preference file: P6809_P6809.prf
Device,speed:    LCMXO2-7000HE,4
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



Timing summary (Setup):
---------------

Timing errors: 6  Score: 281
Cumulative negative slack: 281

Constraints cover 3270002 paths, 1 nets, and 9437 connections (99.1% coverage)

--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
Sun Jan  5 08:23:43 2014

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf 
Design file:     P6809_P6809.ncd
Preference file: P6809_P6809.prf
Device,speed:    LCMXO2-7000HE,m
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



Timing summary (Hold):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 3270002 paths, 1 nets, and 9437 connections (99.1% coverage)



Timing summary (Setup and Hold):
---------------

Timing errors: 6 (setup), 0 (hold)
Score: 281 (setup), 0 (hold)
Cumulative negative slack: 281 (281+0)
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------

Total time: 0 secs 

bitgen -f "P6809_P6809.t2b" -w "P6809_P6809.ncd" -jedec "P6809_P6809.prf"


BITGEN: Bitstream Generator Diamond (64-bit) 2.2.0.101
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.


Loading design for application Bitgen from file P6809_P6809.ncd.
Design name: CC3_top
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-7000HE
Package:     TQFP144
Performance: 4
Loading device for application Bitgen from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
Package Status:                     Final          Version 1.36
Performance Hardware Data Status:   Final)         Version 23.4

Running DRC.
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.
INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
DRC detected 0 errors and 0 warnings.
Reading Preference File from P6809_P6809.prf...

Preference Summary:
+---------------------------------+---------------------------------+
|  Preference                     |  Current Setting                |
+---------------------------------+---------------------------------+
|                         RamCfg  |                        Reset**  |
+---------------------------------+---------------------------------+
|                     MCCLK_FREQ  |                         2.08**  |
+---------------------------------+---------------------------------+
|                  CONFIG_SECURE  |                          OFF**  |
+---------------------------------+---------------------------------+
|                      JTAG_PORT  |                       ENABLE**  |
+---------------------------------+---------------------------------+
|                       SDM_PORT  |                      DISABLE**  |
+---------------------------------+---------------------------------+
|                 SLAVE_SPI_PORT  |                      DISABLE**  |
+---------------------------------+---------------------------------+
|                MASTER_SPI_PORT  |                      DISABLE**  |
+---------------------------------+---------------------------------+
|                       I2C_PORT  |                      DISABLE**  |
+---------------------------------+---------------------------------+
|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
+---------------------------------+---------------------------------+
|                  CONFIGURATION  |                          CFG**  |
+---------------------------------+---------------------------------+
|                COMPRESS_CONFIG  |                           ON**  |
+---------------------------------+---------------------------------+
|                        MY_ASSP  |                          OFF**  |
+---------------------------------+---------------------------------+
|               ONE_TIME_PROGRAM  |                          OFF**  |
+---------------------------------+---------------------------------+
|                 ENABLE_TRANSFR  |                      DISABLE**  |
+---------------------------------+---------------------------------+
|                  SHAREDEBRINIT  |                      DISABLE**  |
+---------------------------------+---------------------------------+
 *  Default setting.
 ** The specified setting matches the default setting.


Creating bit map...
 
Bitstream Status:   Final           Version 1.83
 
Saving bit stream in "P6809_P6809.jed".
 
===========
UFM Summary
===========
UFM Size:        2046 Pages (128*2046 Bits)
UFM Utilization: General Purpose Flash Memory
 
Available General Purpose Flash Memory: 2046 Pages (Page 0 to Page 2045)
Initialized UFM Pages:                     0 Page