Subversion Repositories 6809_6309_compatible_core

Running in Lattice mode


Starting:    C:\lscc\diamond\3.1_x64\synpbase\win64\mbin\synbatch.exe
Install:     C:\lscc\diamond\3.1_x64\synpbase
Date:        Sun Jul 06 07:46:25 2014
Version:     I-2013.09L 

Arguments:   -product synplify_pro  -batch P6809_P6809_synplify.tcl
ProductType: synplify_pro






log file: "C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809.srr"





Running proj_1|P6809


Running: Compile on proj_1|P6809


Running: Compile Process on proj_1|P6809


Running: Compile Input on proj_1|P6809

Copied C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\synwork\P6809_P6809_comp.srs to C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809.srs

compiler Completed with warnings
Return Code: 1
Run Time:0h:00m:04s


Copied C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809.srr to C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809.srf

Complete: Compile Process on proj_1|P6809


Running: Premap on proj_1|P6809

premap Completed with warnings
Return Code: 1
Run Time:0h:00m:01s


Complete: Compile on proj_1|P6809


Running: Map on proj_1|P6809


Running: Map & Optimize on proj_1|P6809

fpga_mapper Completed with warnings
Return Code: 1
Run Time:0h:00m:18s


Complete: Map on proj_1|P6809

Copied C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809.srr to C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809.srf

Complete: Logic Synthesis on proj_1|P6809

TCL script complete: "P6809_P6809_synplify.tcl"

exit status=0


exit status=0


Save changes for project:
C:\02_Elektronik\020_V6809\trunk\synlog file: "C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809.srr"



Running P6809_syn|P6809

Running: Compile on P6809_syn|P6809

Running: Compile Process on P6809_syn|P6809

Running: Compile Input on P6809_syn|P6809
Copied C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\synwork\P6809_comp.srs to C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809.srs
compiler Completed with warnings
Return Code: 1
Run Time:0h:00m:04s

Complete: Compile Process on P6809_syn|P6809

Running: Premap on P6809_syn|P6809
premap Completed with warnings
Return Code: 1
Run Time:0h:00m:01s

Complete: Compile on P6809_syn|P6809

Running: Map on P6809_syn|P6809

Running: Map & Optimize on P6809_syn|P6809
fpga_mapper Completed with warnings
Return Code: 1
Run Time:0h:00m:22s

Complete: Map on P6809_syn|P6809
Complete: Logic Synthesis on P6809_syn|P6809
Opening object source file c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v
Opening object source file c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v
Opening object source file c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v
Opening object source file c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v
exit status=0