URL
https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
Subversion Repositories 6809_6309_compatible_core
[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809.ldf] - Rev 6
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<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="2.0" title="P6809" device="LCMXO2-7000HE-4TG144C" synthesis="synplify" default_implementation="P6809">
<Options/>
<Implementation title="P6809" dir="P6809" description="P6809" default_strategy="Strategy1">
<Options def_top="CC3_top"/>
<Source name="CC3_top.v" type="Verilog" type_short="Verilog">
<Options top_module="CC3_top"/>
</Source>
<Source name="../../rtl/verilog/alu16.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../rtl/verilog/decoders.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../rtl/verilog/defs.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../rtl/verilog/MC6809_cpu.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../rtl/verilog/regblock.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="bios2k.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
<Source name="P6809.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="P68091.sty"/>
</BaliProject>
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