Subversion Repositories 6809_6309_compatible_core

Release 10.1 Map K.31 (lin)
Xilinx Map Application Log File for Design 'CC3_top_x'

Design Information
------------------
Command Line   : map -ise
/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise -intstyle ise
-p xc2s100-pq208-5 -cm area -pr off -k 4 -c 100 -tx off -o CC3_top_x_map.ncd
CC3_top_x.ngd CC3_top_x.pcf 
Target Device  : xc2s100
Target Package : pq208
Target Speed   : -5
Mapper Version : spartan2 -- $Revision: 1.46 $
Mapped Date    : Wed Dec 25 11:42:53 2013

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    6
Logic Utilization:
  Number of Slice Flip Flops:       301 out of  2,400   12%
  Number of 4 input LUTs:         2,239 out of  2,400   93%
Logic Distribution:
    Number of occupied Slices:                       1,198 out of  1,200   99%
    Number of Slices containing only related logic:  1,198 out of  1,198  100%
    Number of Slices containing unrelated logic:         0 out of  1,198    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:        2,291 out of  2,400   95%
      Number used as logic:                     2,239
      Number used as a route-thru:                 52
   Number of bonded IOBs:            26 out of    140   18%
   Number of Block RAMs:              1 out of     10   10%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Peak Memory Usage:  148 MB
Total REAL time to MAP completion:  2 secs 
Total CPU time to MAP completion:   2 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "CC3_top_x_map.mrp" for details.